74LS139 DECODER Search Results

74LS139

Abstract: demultiplexer truth table LS 74LS139 Truth table of 1 to 16 demultiplexer LS139 74ls139 datasheet SN54/74LS139 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
Contextual Info: SN54/74LS139 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

demultiplexer truth table

Abstract: 74ls139 datasheet 74ls139 decoder SN54/74LS139 transistor motorola 236 LS139 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS139 application
Contextual Info: SN54/74LS139 DUAL 1-OF-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder /Demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

pin diagram of ic 74ls139

Abstract: decoder 3-8 74ls with nor gate 74ls139 motorola ttl application TTL IC 74
Contextual Info: MOTOROLA SN54/74LS139 DUAL 1-0F-4 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 Decoder/D e­ multiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW Outputs. Each

74ls139 decoder pin configuration

Abstract: SP74HCT139N 74LS139 SP74HCT139J 74LS139 pin configuration with
Contextual Info: SPI SP74HCT139 DECODER/DEMULTIPLEXER FEATURES • Designed for high performance memory decoders in microprocessor systems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin com patible with 74LS139 ■ SPI CMOS technology

pin diagram of ic 74ls139

Abstract: 74LS139 74LS
Contextual Info: Signetics 74LS139, S139 Decoders/Demultiplexers Dual 1-of-4 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for higher performance

74LS139 pin configuration with

Abstract: 74LS139 74ls139 decoder pin configuration 74ls139 decoder 54LS 74LS
Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Pin Configuration V çç SELECT DATA OUTPUTS ENABLE^_ _ _

Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _

Contextual Info: GD54/74LS139 DUAL 2-TO-4-UNE DECODERS/DEMULTIPLEXERS Feature • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Schottky Clamped for High Performance Pin Configuration SELECT V çç 25 2A 2B DATA OUTPUTS 2VQ 2V1 2Y2

pin diagram of ic 74ls139

Abstract: LS 74LS139 74LS139 74ls139 decoder 74ls139 decoder pin configuration decoders 3*8
Contextual Info: 7 4 LS1 3 9 , S139 Decoders/Demultiplexers S ig n e t ic s Dual 1-of-4 Decoder/Demultiplexer Product Specification Logic Products FEATURES TYPICAL PROPAGATION DELAY ENABLE AT 2 LOGIC LEVELS TYPICAL SUPPLY CURRENT (TOTAL) 74LS139 19ns 6.8mA 74S139 6ns 60mA

LS139

Abstract: LS138 LS138-LS139 74LS139 DM74LS139N
Contextual Info: LS138-LS139 National Semiconductor 54 LS138/DM 54LS138/DM 74LS138, 54 LS139/DM 54LS139/DM 74LS139 Decoders/Demultiplexers General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing appli­

Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The HD74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

SP74SC139N

Abstract: 74ls139 decoder pin configuration 74LS139 SP74SC139F E332A
Contextual Info: / SP74SC139 DECODER/DEMULTIPLEXER PIN CO NFIGURATIO N 1G [ T v cc 1A [T Ï3 2G FEATURES • Designed for high performance memory decoders in microprocessor sytems ■ Two independent 2 to 4 line Decoders/ Demultiplexers with inverted outputs ■ Pin compatible with 74LS139

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

Contextual Info: LS TTL DN74LS Series DN74LS139 DN74LS139 Dual 2 -lin e to 4 -lin e Decoders / Demultiplexers H Description P -2 D N 74LS139 contains tw o 2-bit binary to quaternary de­ coder/dem ultiplexer circuits, each w ith independent enable input term inals. • Features

74LS139

Abstract: 74l513 demultiplexer 74ls 74ls signetics pin diagram of 74LS 74LS 74S139 93L21 N74LS139D N74LS139N
Contextual Info: 74LS139, S139 Signetics Decoders/Demultiplexers Dual 1-of-4 D e c o d e r/D e m u ltip le x e r Product Specification Logic Products FEATURES • Demultiplexing capability • Two independent 1-of-4 decoders • Multifunction capability • Replaces 9321 and 93L21 for

D133

Abstract: 74ls139 TTL 9334 74LS152 PIN 74LS42 7442 pin diagram 93L01 74156 ttl 74155 D132
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 T12 T11 T10 T9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

pin diagram decoder 74154

Abstract: 74155 decoder 74LS247 TTL 7448 74LS42 cmos decoder 7448 input 16 pin 7SEG COM ANODE 74151 PIN DIAGRAM cI 74150 D133
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

Contextual Info: 139 139 CONNECTION DIAGRAM PINOUT A // 54S/74S139 d / 6 b c \/54LS/74LS139 6 i o ^ ' f ° 7 DUAL 1-0F-4 DECODER D E S C R IP TIO N — The ’139 is a high speed dual 1-of-4 decoder/dem ultiplexer. The device has tw o independent decoders, each accepting tw o inputs

74LS139

Abstract: M16A M16D MM74HC139 MM74HC139M MM74HC139MTC MM74HC139SJ MTC16 diode D254
Contextual Info: Revised February 1999 E M IC O N D U C T O R T M MM74HC139 Dual 2-To-4 Line Decoder General Description equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and T he M M 74H C 139 d ecoder utilizes advanced silicon-gate

74191 8 bit

Abstract: D flip-flop 74175 pin 74LS152 74155 D134 D132 74155 PIN DIAGRAM 7442 logic diagram D133 93L21
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

pin diagram of 74LS191

Abstract: TTL 7452 74155 74190 74151 74151 PIN DIAGRAM D132 74LS151 Logic DIAGRAM 74ls156 74191 state diagram
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 T12 T11 T10 T9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

transistor d133

Abstract: Decoder BCD 7 seg ttl 7442 transistor 6B 7-seg ANODE COMMON 74155 74LS247 pin diagram of 74LS247 ttl 74191 75491
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

7448 decoder

Abstract: ID 9302 Fairchild 74190 pin diagram decoder 7447 TTL 7448 74LS47 74LS47 pin TTL 7446 decoder 74LS47 decoder 7448
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 G N D = Pin 8 Vcc = Pin 16 G N D = Pin 8

74HC139M

Abstract: 74hc139n
Contextual Info: A s e m I R C i c o n H d u S eptem ber 1983 I L D Revised February 1999 c t o r MM74HC139 Dual 2-To-4 Line Decoder equivalent to the 74LS139. All inputs are protected from dam age due to static discharge by diodes to V qq and General Description The M M 74H C 139 deco d e r utilizes advanced silicon-gate