74LS10 FUNCTION TABLE Search Results

Contextual Info: LS10 ZgkNational JQflSemiconductor 54LS10/DM54LS10/DM 74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. _ • Alternate Military/Aerospace device 54LS10 is available. Contact a National Semiconductor Sales Office/

74LS10 pin configuration

Contextual Info: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9

TTL 7410

Abstract: 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics
Contextual Info: Signetics I 7410, 7411, LS10, LS11 S10, S11 Gates Logic Products • Triple Three-Input NAND '10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S1Û 3ns 12mA 7411 10ns

TTL 7411

Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA

TTL 7410

Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

LM 7410

Contextual Info: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns

Contextual Info: AVG Semiconductors DDiT Technical Data DV74LS10 DV74ALS10A Triple 3-Input NAND Gates N Suffix Plastic DIP AVG-001 Case This device contains three independent gates, each of which performs the logic NAND function. AVG’s LS operates over extended Vcc from 4.5 to 5.5 V

74HC10

Abstract: 74LS10 truth table
Contextual Info: r z 7 S G S -T H O M S O N Ä 7# M 54H C 10 M74HC10 TRIPLE 3-INPUT NAND GATE • HIGHSPEED tPD = 6 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 HA (MAX.) AT Ta = 25 "C ■ HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

74hct10m

Contextual Info: fZ7 SGS-THOMSON M54HCT1o M74HCT10 Ä 7# TRIPLE 3-INPUT NAND GATE • HIGHSPEED tPD = 11 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 uA (MAX.) AT T a = 25 *C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX) ■ OUTPUT DRIVE CAPABILITY

74HCT10

Contextual Info: r Z 7 S G S -T H O M S O N È M 54H C T10 M74HCT10 TRIPLE 3-INPUT NAND GATE • HIGHSPEED tpD = 11 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 |iA (MAX.) AT Ta = 25 "C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX) ■ OUTPUT DRIVE CAPABILITY

74LS10 function table

Contextual Info: TOSHIBA TC74HC1QÄP/AF/AFN Triple 3-Input NAND Gate The TC74HC1OA is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Contextual Info: S G S -T H O M S O N iD œ a iÊ T IM D Ê I M54HC10 M74HC10 TRIPLE 3-INPUT NAND GATE • HIGHSPEED tpD = 6 ns TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 1 HA (MAX.) AT TA = 25 "C ■ HIGH NOISE IMMUNITY V nih = V nil = 28 % Vcc (MIN.) ■ OUTPUT DRIVE CAPABILITY

IC AND GATE 7408 specification sheet

Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
Contextual Info: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format

74ls163 function table

Contextual Info: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs

74LS10

Abstract: DIP14-P-300-2 TC74HC10A TC74HC10AFN TC74HC10AP
Contextual Info: TOSHIBA TC74HC10AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC10AP, TC74HC10AF, TC74HC10AFN Note The JEDEC SOP (FN) is not available in Japan. TRIPLE 3 -IN P U T NAND GATE The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

Contextual Info: - TC74HC10AP/AF/AFN TRIPLE 3-INPUT NAND GATE The TC74HC10A is a high speed CMOS 3-IN P U T N AN D G A TE fabricated w ith silicon gate C^M O S technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m ain tain in g the CMOS low power

of IC 74ls10

Abstract: triple3-input nand gate M54HCT10 M54HCT10F1R M74HCT10 M74HCT10B1R M74HCT10C1R M74HCT10M1R 74HCT 3-input OR gate 74ls10 IC
Contextual Info: M54HCT10 M74HCT10 TRIPLE 3-INPUT NAND GATE . . . . . . . HIGH SPEED tPD = 11 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

M54HCT10

Abstract: M54HCT10F1R M74HCT10 M74HCT10B1R M74HCT10C1R M74HCT10M1R 74ls10 IC
Contextual Info: M54HCT10 M74HCT10 TRIPLE 3-INPUT NAND GATE . . . . . . . HIGH SPEED tPD = 11 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

Contextual Info: TC74HC10AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC10AP,TC74HC10AF,TC74HC10AFN Triple 3-Input NAND Gate The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

74HC10

Abstract: M54HC10 M54HC10F1R M74HC10 M74HC10B1R M74HC10C1R M74HC10M1R 74HC10 equivalent
Contextual Info: M54HC10 M74HC10 TRIPLE 3-INPUT NAND GATE . . . . . . . . HIGH SPEED tPD = 6 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

of IC 74ls10

Contextual Info: TC74HC10AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC10AP,TC74HC10AF,TC74HC10AFN Triple 3-Input NAND Gate The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

74LS10

Abstract: DIP14-P-300-2 TC74HC10A TC74HC10AF TC74HC10AFN TC74HC10AP 74LS10 truth table
Contextual Info: TO SH IBA TC74HC10AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC10AP, TC74HC10AF, TC74HC10AFN Note The JEDEC SOP (FN) is not available in Japan. TRIPLE 3 -IN PU T NAND GATE The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology.

of IC 74ls10

Contextual Info: TC74HC10AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC10AP,TC74HC10AF,TC74HC10AFN Triple 3-Input NAND Gate The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

CI 74ls10

Abstract: 74HCT10
Contextual Info: S G S -T H O M S O N jL iM s iO (g S M54HCTio M 74H C T10 TRIPLE 3-INPUT NAND GATE • HIG HSPEED tpD = 11 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION lec = 1 |iA (MAX.) AT T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2 V (MIN.) V il = 0.8V (MAX)