74LVQ00 Search Results

Contextual Info: S E M IC O N D U C T O R 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input N AND gates. • Ideal for low pow er/low noise 3.3V applications ■ Guaranteed sim ultaneous sw itching noise level and dynam ic threshold perform ance

74LVQ00

Abstract: 74LVQ00M 74LVQ00T TSSOP14
Contextual Info: 74LVQ00  QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ00

Abstract: 74LVQ00SC 74LVQ00SJ M14A M14D
Contextual Info: + SEMICONDUCTOR 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input N AND gates. • Ideal for low pow er/low noise 3.3V applications ■ G uaranteed sim ultaneous sw itching noise level and d ynam ic threshold perform ance

74LVQ00

Abstract: 74LVQ00M 74LVQ00T TSSOP14
Contextual Info: 74LVQ00 QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ00

Abstract: 74LVQ00SC 74LVQ00SCX 74LVQ00SJ 74LVQ00SJX M14A M14D s070 DD0-2
Contextual Info: National Semiconductor 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance

Contextual Info: Æ T S G S -T H O M S O N D lsi S IILICTIs! iD©S 74LVQ00 QUAD 2-INPUT NAND GATE . HIGH SPEED: tPD = 5.5 ns (TYP.) at V c c = 3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Ice = 2 |xA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at V c c = 3.3V

LH 036

Abstract: 74LVQ00
Contextual Info: S G S -TH O M S O N G l 74LVQ00 IU QUAD 2-INPUT NAND GATE . HIGH SPEED: tpD = 5.5 ns TYP. at Vcc = 3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Icc = 2 nA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0.3 V (TYP.) at Vcc = 3.3V . 75i2 TRANSMISSION LINE DRIVING

KHN 10

Abstract: 74LVQ00 74LVQ00M 74LVQ00T TSSOP14 truth table NAND gate 74
Contextual Info: SGS-THOMSON 74LVQ00 M IM i[Li gïïlHΩiD(3S Q UAD 2-IN PUT NAND GATE . HIGH SPEED: tPD = 5.5 ns (TYP.) at V Cc =3.3V . COMPATIBLE WITH TTL OUTPUT . LOW POWER DISSIPATION: Icc = 2 |xA (MAX.) at T a = 25 °C . LOW NOISE: V o lp = 0.3 V (TYP.) at V Cc = 3.3V

TSSOP14

Abstract: SO-14 TSSOP-14 SO14 SO-20 74LVQ574 74LVQ373
Contextual Info: LOGIC CIRCUITS LOW VOLTAGE HIGH SPEED CMOS - LVQ 74LVQ SERIES RECOMMENDED OPERATING CONDITIONS Symbol VCC VI TA Parameter Supply Voltage Input Voltage Operating Temperature 74 Series Type 74LVQ00 74LVQ02 74LVQ04 74LVQ08 74LVQ125 74LVQ138 74LVQ14 74LVQ157

Contextual Info: bME I • b5011S2 007b371 32h H N S C 1 LVQOO 03 National m iM , Semiconductor 54LVQ/74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The 'LVQOO contains four 2-input NAND gates. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and

d flip flop

Abstract: D Flip-Flop 74LVQ00 74LVQ02 74LVQ04 74LVQ08 74LVQ125 74LVQ138 74LVQ14 74LVQ151
Contextual Info: Logic Products by Family LVQ Products Logic Product Function Product Description Package Voltage Node 74LVQ00 Gate Low Voltage Quad 2-Input NAND Gate SOIC SOP 2.7 3.3 74LVQ02 Gate Low Voltage Quad 2-Input NOR Gate SOIC SOP 2.7 3.3 74LVQ04 Inverter Low Voltage Hex Inverter

74LVQ00

Contextual Info: 74LVQ00 QUAD 2-INPUT NAND GATE . HIGH SPEED: tPD = 5.5 ns TYP. at Vcc = 3.3V • COMPATIBLE WITH TTL OUTPUTS . LOW POWER DISSIPATION: Ice = 2 nA (MAX.) at T a = 25 °C . LOW NOISE: V olp = 0 .3 V (TYP.) at V c c = 3 .3 V ■ 75Q TRANSMISSION LINE DRIVING

74LVQ00

Abstract: 74LVQ00M 74LVQ00MTR 74LVQ00TTR TSSOP14
Contextual Info: 74LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

74LVQ00

Abstract: 74LVQ00MTR 74LVQ00TTR TSSOP14
Contextual Info: lvq00.fm Page 1 Thursday, July 29, 2004 2:28 PM 74LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C

Contextual Info: LVQOO £3 National mm Semiconductor 54LVQ/74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The ’LVQOO contains four 2-inpul NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and

74LVQ00

Abstract: 74LVQ00M 74LVQ00MTR 74LVQ00TTR TSSOP14
Contextual Info: 74LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

Contextual Info: S E M IC O N D U C T O R tm 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains fo u r 2-input NAND gates. • ideal fo r low pow er/low noise 3.3V applications ■ G uaranteed sim ultaneous sw itching noise level and

Contextual Info: October 1995 Semiconductor 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance

74LVQ00

Contextual Info: 74LVQ00 QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5 ns TYP. at VCC = 3.3V COMPATIBLE WITH TTL OUTPUT LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVG

Contextual Info: LVQOO National Semiconductor 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance

74LVQ00

Abstract: 74LVQ00MTR 74LVQ00TTR TSSOP14
Contextual Info: lvq00.fm Page 1 Thursday, July 29, 2004 2:28 PM 74LVQ00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C

74LVQ00

Abstract: 74LVQ00SC 74LVQ00SJ M14A M14D
Contextual Info: Revised April 2001 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQ00 contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance

T4-1T

Abstract: 74LCX574 AD6640 AD6640AST AD9631 AD96687 OP279 AD6620
Contextual Info: a FEATURES 65 MSPS Minimum Sample Rate 80 dB Spurious-Free Dynamic Range IF Sampling to 70 MHz 710 mW Power Dissipation Single 5 V Supply On-Chip T/H and Reference Twos Complement Output Format 3.3 V or 5 V CMOS Compatible Output Levels APPLICATIONS Cellular/PCS Base Stations

U204

Abstract: AD6600 AD6600AST AD6620 AD6630 AN-501 IS-136 J201
Contextual Info: a Dual Channel, Gain-Ranging ADC with RSSI AD6600 two input channels, each with 1 GHz input amplifiers and 30 dB of automatic gain-ranging circuitry. Both channels are sampled with a 450 MHz track-and-hold followed by an 11-bit, 20 MSPS analog-to-digital converter. Digital RSSI outputs, an