74LVC10 Search Results
74LVC10 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| SN74LVC10ADBR | Texas Instruments | Triple 3-Input Positive-NAND Gate 14-SSOP -40 to 125 |
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| SN74LVC10ANSR | Texas Instruments | Triple 3-Input Positive-NAND Gate 14-SO -40 to 125 |
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| SN74LVC10APWT | Texas Instruments | Triple 3-Input Positive-NAND Gate 14-TSSOP -40 to 125 |
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| SN74LVC10ADR | Texas Instruments | Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 |
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| SN74LVC10ADG4 | Texas Instruments | Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 125 |
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74LVC10 Datasheets (82)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| 74LVC10 | Philips Semiconductors | Triple 3-input NAND gate | Original | 96.07KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109 | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Original | 105.56KB | 10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109A | Integrated Device Technology | 3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIGGER, 5V TOLERANT I-O | Original | 139.93KB | 6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109A | Philips Semiconductors | Dual J-k Positive Edge Triggered Flip-flop With Clear and Preset | Original | 111.05KB | 10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D | Philips Semiconductors | Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 110.99KB | 10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 31.8KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 177.39KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 185.88KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D,112 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Tube | Original | 104.88KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D,112 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch | Original | 130.2KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D,118 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1.2-3.6; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13" | Original | 104.88KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109D,118 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SO-16, FF/Latch | Original | 130.2KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB | Philips Semiconductors | Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 110.99KB | 10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 31.8KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 177.39KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 185.88KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB,112 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Tube | Original | 104.88KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB,112 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch | Original | 130.2KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB,118 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" | Original | 104.88KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 74LVC109DB,118 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch | Original | 130.2KB | 17 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
74LVC10 Price and Stock
NXP Semiconductors 74LVC10APW,118NAND Gate 3-Element 3-IN CMOS 14-Pin TSSOP T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC10APW,118 | 50,000 | 1,676 |
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| 74LVC10APW,118 | 7,500 | 1,676 |
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| 74LVC10APW,118 | 2,006 | 1,676 |
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74LVC10APW,118 | 69,888 | 1 |
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Nexperia 74LVC10AD,118NAND Gate 3-Element 3-IN 14-Pin SO T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC10AD,118 | 25,000 | 1,586 |
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| 74LVC10AD,118 | 5,000 | 1,586 |
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74LVC10AD,118 | Tape & Reel | 24 Weeks | 7,500 |
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74LVC10AD,118 | 30,000 | 1 |
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74LVC10AD,118 | 1 |
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74LVC10AD,118 | 26 Weeks | 2,500 |
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Integrated Device Technology Inc 74LVC109AXTPY74LVC109AXTPY |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC109AXTPY | 19,092 | 2,104 |
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Buy Now | ||||||
NXP Semiconductors 74LVC10AD,112NAND Gate 3-Element 3-IN CMOS 14-Pin SO Bulk |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC10AD,112 | 17,964 | 1,092 |
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| 74LVC10AD,112 | 7,441 | 1,092 |
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Buy Now | |||||||
NXP Semiconductors 74LVC10AD,118NAND Gate 3-Element 3-IN CMOS 14-Pin SO T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC10AD,118 | 15,000 | 1,586 |
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| 74LVC10AD,118 | 5,000 | 1,586 |
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| 74LVC10AD,118 | 2,500 | 1,586 |
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74LVC10AD,118 | 22,973 | 1 |
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74LVC10 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: 74LVC10A Triple 3-input NAND gate Rev. 5 — 17 November 2011 Product data sheet 1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. |
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74lvc10ajesd8-c/jesd36jesd22-a114f | |
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Contextual Info: Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V The 74LVC1G9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. |
OCR Scan |
74lvc10974lvc1g974hc/hct109sv00904 | |
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Contextual Info: IM P \ P -H n H IE '1 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook Philips Semiconductors 1998 Apr 28 PHILIPS Philips Semiconductors Product specification Dual JR flip-flop with set and reset; positive-edge trigger |
OCR Scan |
74lvc10974hc/hct10974lvc109t | |
74LVC109
Abstract: 74LVC109A 74LVC109D 74LVC109DB 74LVC109PW SSOP16 TSSOP16 MNA860
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74lvc10974lvc109asca76r20/04/pp18+6 | |
74LVC10A
Abstract: 74LVC10APW MS-012AB SSOP14 TSSOP14 jedec MO-150AB 74LVC1
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OCR Scan |
74lvc10a74lvc1tssop14sqt402-1+5 | |
sot762 footprint
Abstract: 74LVC10A 74LVC10ABQ 74LVC10AD 74LVC10ADB 74LVC10APW DHVQFN14 SSOP14 TSSOP14
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74lvc10aeia/jesd22-a114-asca75613508/03/pp16+8 | |
74LVC109Contextual Info: 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Rev. 5 — 29 November 2012 Product data sheet 1. General description The 74LVC109A is a dual positive edge triggered JK flip-flop featuring: • • • • individual J and K inputs clock CP inputs |
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74lvc10974lvc109a | |
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Contextual Info: Product Specification Philips Semiconductors Triple 3-input NAND gate QUICK REFERENCE DATA GND = 0 V; Tsmb = 25°C; tr = t, < 2.5 ns FEATURES • • • • • • • 74LVC10 Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1 A. |
OCR Scan |
74lvc10 | |
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Contextual Info: INTEGRATED CIRCUITS 74LVC10 Triple 3-input NAND gate Product specification Replaces data sheet of 1996 Feb IC24 Data Handbook Philips Semiconductors 1997 Apr 28 PHILIPS Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10 FEATURES |
OCR Scan |
74lvc10 | |
NSP 055
Abstract: 74LVC109 9l reset 74LVC109PW
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OCR Scan |
74lvc109sqt403-1mo-153nsp 055+2 | |
74LVC10
Abstract: 74LVC10D 74LVC10DB 74LVC10PW
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OCR Scan |
74lvc1074lvc10d74lvc10db74lvc10pw | |
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Contextual Info: 74LVC10A Triple 3-input NAND gate Rev. 5 — 17 November 2011 Product data sheet 1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. |
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74lvc10ajesd8-c/jesd36jesd22-a114fjesd22-a115-b+1 | |
DHVQFN14
Abstract: 74LVC10A 74LVC10ABQ 74LVC10AD 74LVC10ADB 74LVC10APW SSOP14 TSSOP14
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74lvc10aeia/jesd22-a114-aeia/jesd22-a115-aot402-1+8 | |
74LVC10A
Abstract: 74LVC10APW SSOP14
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74lvc10a74lvc10apwssop14 | |
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dhvqfn14
Abstract: SV00418 04482
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74lvc10adhvqfn14sv0041804482 | |
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Contextual Info: 74LVC10A Triple 3-input NAND gate 1998 Apr 28 Product specification Philips Semiconductors P H IItK PHILIPS Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC1OA FEATURES DESCRIPTION • Wide supply voltage range of 1.2 V to 3,6 V |
OCR Scan |
74lvc10a74lvc1oa74lvc1 | |
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Contextual Info: Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A FEATURES DESCRIPTION • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. The 74LVC10A is a high performance, low power, low voltage, Si |
OCR Scan |
74lvc10a74lvc1oa | |
74LVC10
Abstract: 74LVC10PW
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74lvc1074lvc10pw | |
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Contextual Info: Philips Semiconductors Product Specification Triple 3-input NAND gate FEATURES • • • • • • • 74LVC10 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = t, < 2.5 ns Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1 A. |
OCR Scan |
74lvc10 | |
74LVC109
Abstract: 74LVC109PW
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74lvc10974hc/hct10974lvc109pw | |
TTL 74-series IC LIST
Abstract: 74 Series Logic ICs TTL 74-series IC PO74G74 PO74G04 list cmos ics 49fct32805 49FCT3807 Potato Semiconductor 49FCT3805
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po49fct3802apo49fct3803b700mhzpo49fct3804+15 | |
LCX06
Abstract: LCX16244 SN74LVCR162245A mc74lcx245 Schmitt Trigger lcx162245 74LVC162244A LCX04 LCX843 LCXH162245 lcx32
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lcx00lcx02lcx04lcxu04+14 | |
5555 FAIRCHILD optocoupler
Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
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scyb017aa0102035555 fairchild optocouplermc74hc374n+8 | |
74LVC05
Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
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32-bitcompatibilit-785074lvc057400 datasheet 2-input nand gate+8 | |