74LVC109DB Search Results
74LVC109DB Datasheets (11)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| 74LVC109DB | Philips Semiconductors | Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger | Original | 110.99KB | 10 | ||
| 74LVC109DB | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 31.8KB | 1 | ||
| 74LVC109DB | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 177.39KB | 5 | ||
| 74LVC109DB | Philips Semiconductors | Dual JK flip-flop with set and reset, positive-edge trigger | Scan | 185.88KB | 5 | ||
| 74LVC109DB,112 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Tube | Original | 104.88KB | 18 | ||
| 74LVC109DB,112 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch | Original | 130.2KB | 17 | ||
| 74LVC109DB,118 | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" | Original | 104.88KB | 18 | ||
| 74LVC109DB,118 | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch | Original | 130.2KB | 17 | ||
| 74LVC109DB-T | NXP Semiconductors | Dual JK(not) flip-flop with set and reset; positive-edge trigger - Description: 3.3V Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 330 MHz; Logic switching levels: TTL ; Output drive capability: +/- 24 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 4.0@3.3V ns; Voltage: 1-2-3.6 | Original | 104.88KB | 18 | ||
| 74LVC109DB-T | NXP Semiconductors | 74LVC109 - IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP2-16, FF/Latch | Original | 130.2KB | 17 | ||
| 74LVC109DB-T | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 31.8KB | 1 |
74LVC109DB Price and Stock
NXP Semiconductors 74LVC109DB,118Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SSOP T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC109DB,118 | 5,000 | 746 |
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74LVC109DB,118 | 5,000 | 1 |
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Philco/Philips 74LVC109DB,118Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SSOP T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC109DB,118 | 2,999 | 1 |
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Philips Semiconductors 74LVC109DB,118 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC109DB,118 | 1,600 |
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| 74LVC109DB,118 | 799 |
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NXP Semiconductors 74LVC109DB,112J-Kbar Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC109DB,112 | 5,224 |
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74LVC109DB Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
5555 FAIRCHILD optocoupler
Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
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scyb017aa0102035555 fairchild optocouplermc74hc374n+8 | |
74LVC109
Abstract: 74LVC109A 74LVC109D 74LVC109DB 74LVC109PW SSOP16 TSSOP16 MNA860
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Original |
74lvc10974lvc109asca76r20/04/pp18+6 | |
74LVC109Contextual Info: 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Rev. 5 — 29 November 2012 Product data sheet 1. General description The 74LVC109A is a dual positive edge triggered JK flip-flop featuring: • • • • individual J and K inputs clock CP inputs |
Original |
74lvc10974lvc109a | |
74LVC109
Abstract: 74LVC109D 74LVC109DB 74LVC109PW
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OCR Scan |
74lvc10974hc/hct109711052b74lvc109d+2 | |
74LVC109
Abstract: 74LVC109D 74LVC109DB 74LVC109PW
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OCR Scan |
74lvc10974hc/hct109ci075474lvc109d+2 | |
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Contextual Info: Product Specification Philips Semiconductors Dual JK flip-flop with set and reset; positive-edge trigger FEATURES • • • • • • • Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1 A. Inputs accept voltages upto |
OCR Scan |
74lvc109 | |
74LVC109
Abstract: 1RDD 1712J
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OCR Scan |
74lvc1091rdd1712j | |
MC0628R
Abstract: 40373 74hc14n equivalent 4046 application note philips HCF4060BE HCF4017BE SN74121 application note MC74HC373DW mc0628 HCF4053BE
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Original |
scyb017at74alvc3237474cbtlv16211sn74cbtd16211+14 | |
5555 FAIRCHILD optocoupler
Abstract: DM74LS75N MC74HC373DW 74hc14n equivalent HCF4060BE 40373 NC7S125M5X datasheet 14543 motorola 14049 CD40106BE
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Original |
scyb017aa0102035555 fairchild optocouplerdm74ls75n+8 |