74LS21 Search Results

Contextual Info: 54/7421 54H/74H21 54LS/74LS21 ORDERING CODE PIN CONFIGURATIONS See Section 9 for further Package and Ordering Information. PACKAGES PIN CONF. COMMERCIAL RANGES MILITARY RANGES VCC = 5V ± 5%; Ta = 0°C to *70°C VCC = 5V ± 10"/.; Ta = -55°C to *125°C

74LSOO

Contextual Info: H D 74LS21. Dual 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item T a = - 20~ + 75°C) min T e s t Conditions Symbol ‘yp* max Unit VlH 2 .0 - - V VlL - - 0 .8 V V Input voltage VOH Vcc = 4.75V , Vih = 2V, Ioh = —400/iA

74ls21 IC

Contextual Info: SANYO SEMICONDUCTOR CORP I EE D LC74HC21 PU 1 im a n n DQoat .33 a CMOS High-Speed Standard Logic LC74HC Series 3003a Dual 4-Input AND Gate E 1743C Features • The LC74HC21 consists of 2 identical 4-input AND gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to L S -T T L (74LS21 with the

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

M74LS21P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs 74LS21P DUAL 4 -IN P U T P O S IT IV E AND GATE DESCRIPTION The M 74LS21P c o n ta in in g tw o is a s e m ico n d u c to r 4 -in p u t positive AND in teg rated and c irc u it negative O R gates. FEATURES • H igh b re a k d o w n in p u t voltage V | > 1 5 V

TTL 7421

Abstract: 7421 ttl AND gate TTL 7420 74LS21 PIN CONFIGURATION 7421 pin configuration 7420 pin configuration 74LS gates 7420 nand 74ls gate symbols PIN CONFIGURATION 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

Contextual Info: < 8>MOTOROLA SN54/74LS21 D U A L 4 -IN P U T A N D G A T E ü l u l ü m tu tu l ì LO W PO W ER SC H O T T K Y J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 (Plastic) G U A R A N T E E D OPERATING R A N G E S MIN TYP MAX UNIT vcc SYM B O L Supply Voltage

ls 7421

Abstract: logic gate 7421 AND 74LS21
Contextual Info: NATIONA L S E M C O N D {LOGIC} DEE D I LSQ115E DD^bSt, 1 I 21 T -< /3 -/!T CONNECTION DIAGRAMS PINOUT A 54/7421 54H/74H21 54LS/74LS21 DUAL 4-INPUT POSITIVE AND GATE ORDERING COPE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE Vcc = +5.0 V ±5%, = 0°C to +70° C

TTL 74ls21

Abstract: 751A-02 motorola 74ls21
Contextual Info: SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

74ls21p

Abstract: 7421 Dual 4-input AND gate 74LS21 74H21 7421 54H21DM 54H21FM 54LS21 54LS21FM 74LS21PC
Contextual Info: 21 C O N N E C T IO N D IA G R A M S P IN O U T A /5 4 /7 4 2 1 54H /74H 21 r / ^54LS/74LS21 ^^ DUAL 4-IN P U T POSITIVE AND GATE O R D E R IN G CO D E: See S e ctio n 9 PIN PKGS OUT C O M M E R C IA L G RADE M ILITA R Y G RADE V c c = + 5.0 V ±5%, T a = 0 °C to + 7 0 ° C

TTL 74ls21

Abstract: 74LS21 751A-02
Contextual Info: M MOTOROLA SN54/74LS21 DUAL 4-INPUT AND GATE DU A L 4 -IN P U T AND GATE vcc LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 N SUFFIX PLASTIC CASE 646-06 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES

74LS210

Abstract: SN74LS210 SN54/74LS210 SN74S210 42A12A 74S210 2y2e
Contextual Info: 8-Bit Buffers SN 54/74LS210 S N 54/74S 210 S N 5 4 /7 4 L S 2 4 0 S N 5 4 /7 4 L S 2 4 1 S N 5 4 /7 4 L S 2 4 4 S N 5 4 /7 4 S 2 4 0 S N 5 4 /7 4 S 2 4 1 S N S 4 /7 4 S 2 4 4 Ordering Information Features/ Benefits • Three-slate outputs drive bus lines PART

74LS210

Abstract: 74ls244 latch 74LS344 LS 74LS245 74ls245 sn74s700 SN74S731 74s535 74LS244 54LS340
Contextual Info: 8-Bit Interface Selection Guide 8-Bit Interlace PART NUMBER COMMERCIAL MILITARY SN74LS241 SN 74LS244 SN74LS341 SN 74LS344 SN54LS241 SN54LS244 SN54LS341 SN 54LS344 SN 74LS210 SN 74LS240 SN 74LS310 SN 74LS340 SN 54LS210 SN 54LS240 SN 54LS310 SN 54LS340 SN74S241

74LS21

Abstract: 7421 pin configuration 74LS N7421F N7421N N74H21F N74H21N N74LS21F N74LS21N S5421F
Contextual Info: 54/7421 54H/74H21 54LS/74LS21 ORDERING CODE PIN CONFIGURATIONS See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES = 5V ± 5%; T a = 0°C to *70°C PACKAGES PIN CON F. Plastic DIP Fig. A Fig. A N7421N • N74H21N 74LS21N

TTL 74ls21

Abstract: 74ls21
Contextual Info: g MOTOROLA SN54/74LS21 DUAL 4-INPUT AND GATE DUAL 4-INPUT AND GATE [ÏÏ1 R [ÏÏ1 M N [71 fe i vcc LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 632-08 GND N SUFFIX , D SUFFIX SOIC CASE 751A ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic

74LS21P

Abstract: M74LS21P
Contextual Info: MITSUBISHI LSTTLs 74LS21P DUAL 4 -IN P U T P O S IT IV E AND GATE DESCRIPTION The M 74LS21P c o n ta in in g tw o is a s e m ico n d u c to r 4 -in p u t positive AND in teg rated and c irc u it negative O R gates. FEATURES • H igh b re a k d o w n in p u t voltage V | > 1 5 V

TTL 7421

Abstract: 7421 ttl AND gate 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 pin configuration 7420 SIGNETICS TTL 74LS20
Contextual Info: 7420, 7421, LS20, LS21, S20 Signetics Gates Dual Four-Input NAND 20 AND (’21) Gate Product Specification Logic Products TYPE TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3 ns 8mA 7421 12ns 8mA 74LS21 9ns

7421 AND gate

Abstract: 7421 74LS21 74LS21P 7421 Dual 4-input AND gate 74LS21PC 74LS21DC DC5421 54H21DM 54H21FM
Contextual Info: 21 CO NNECTIO N DIAGRAMS PINOUT A /5 4 /7 4 2 1 i/54H/74H21 r 54LS/74LS21 / m s t - ^ fo f/c a DUAL 4-IN P U T POSITIVE AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V +10%,

74LS21 PIN CONFIGURATION

Abstract: 74LS21 54LS 74LS
Contextual Info: GD54/74LS21 DUAL 4-INPUT POSITIVE AND GATES Description Pin Configuration This device contains two independent 4-input AND gates. It performs the Boolean functions Y = A B C D or Y = A + B + C + D in positive logic. V Cc 2D 2C NC 2B 2A 2Y 1A 1B NC 1C 1D 1Y

ic 7421

Abstract: TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 function ic 7421 TTL 7420 7421 IC ic ttl 7421 pin configuration ic 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification H TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY TYPE 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

74HC21A

Abstract: 74LS211
Contextual Info: -TC74HC21AP/AF/AFN D U A L 4- IN PU T A ND GATE T h e TC 74H C 21A is a h igh speed CM O S 4 - I N P U T A N D G A T E fa b ric a te d w ith silic o n g a te C2M OS tech n ology. It ach ieves the h igh speed op eratio n s im ila r to equ ivalen t L S T T L w hile m a in ta in in g the CM O S low pow er

74HC21A

Contextual Info: TOSHIBA TC74HC21AP/AF/AFN Dual 4-Input and Gate TheTC 74H C 21A is a high speed CMOS 4-INPUT AND GATE fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

SN74H21

Abstract: LS21 SN54H21 SN54LS21 SN74 SN74LS21
Contextual Info: TYPES SN54H21, SN54LS21, SN74H21, 74LS21 DUAL 4-INPUT POSITIVE-AND GATES — REVISED APRIL 1985 S N 5 4 H 2 1 . . . J P AC KA G E S N 5 4 L S 2 1 . . . J OR W P AC KA G E S N 7 4 H 2 1 . . . J O R N P AC KA G E S N 7 4 L S 2 1 . . . D , J OR N P AC KA G E

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES