74298 FUNCTION TABLE Search Results

CD0494

Abstract: 74298 function table 74298 signetics 74298
Contextual Info: 74298, LS298 Signetics Registers Quad 2-Port Register Product Specification Logic Products FEATURES • Fully synchronous operation • Select from two data sources • Buffered, negative edge triggered clock TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

Contextual Info: 74 2 9 8 , LS298 Signetics Registers Quad 2-Port Register Product Specification Logic Products FEATURES • Fully synchronous operation • Select from two data sources • Buffered, negative edge triggered clock TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

Contextual Info: 74 2 9 8 , LS298 Signelics Registers Quad 2-Port Register Product Specification Logic Products FEATURES • Fully synchronous operation • Select from two data sources • Buffered, negative edge triggered clock DESCRIPTION This device is a high-speed Quad 2-Port

ic ttl 74ls

Abstract: 74298 pin diagram of 74LS LS298 ic 74298 1N3064 1N916 74LS 74LS298 N74298N
Contextual Info: 74298, LS298 Signetics Registers Quad 2-Port Register Product Specification Logic Products FEATURES • Fully synchronous operation • Select from two data sources • Buffered, negative edge triggered clock T Y P IC A L P R O P A G A TIO N D E LA Y T Y P IC A L SU P P LY C U R R E N T

7429 TTL

Abstract: IC TTL 7429 74298 application N54298 SN74298 54175 IC 74175 54ls298
Contextual Info: TYPES SN54298, SN54LS298, SN74298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE M ARCH B2 c 1 U l 6 : A2 c 2 15 j A1 c 3 14 : B1 c 4 13 C2 c 5 D2 c 6 D1 c 7 Implement Separate Registers Capable of Parallel Exchange o f Contents Vet Retain External Load Capability

TTL 74139

Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
Contextual Info: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 bcd counter using j-k flip flop diagram Multiplexer 74153 CI 74138
Contextual Info: AUGUST 1984 semiconductor MSM60300, MSM60700, MSM61000 CMOS GATE ARRAYS GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700, and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors

truth table for ic 74138

Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
Contextual Info: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture

ttl 7436

Abstract: IC TTL 7432 ls 7432 IC TTL 74 ls 04 SN74298 functional diagram IC 7432 IC 7432 74298 application multiplexers 74 LS 150
Contextual Info: TTL MSI TYPES SN54298, SN54LS298. SN74298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE B U LL E T IN NO. DL-S 7611747, MARCH 1 9 7 4 -R E V IS E D O C TO BER 1976 I• Selects One of Two 4-Bit Data Sources and Stores Data Synchronously with System dock

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 ic 74151 ic 74148 block diagram MSI IC 74138 decoder
Contextual Info: s I SEMICONDUCTOR GROUP 23E D • t?54E40 G00fl535 1 "T-q2-q \ p a rtII CMOS STANDARD CELL LSI MSM91H000 SERIES ¿U S' This M a terial C o p y r i g h t e d B y Its R e s p e c t i v e M a n u f a c t u r e r O K I SEMICONDUCTOR GROUP 23E D ■ b72M240 DGGÔ23b G

7486 XOR gate

Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
Contextual Info: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­

7483 4-bits parallel adder

Abstract: ttl 74147 ttl 7442 ttl 7483 enc8to3 priority encoder 16 to 4 74148 TTL 74138 TTL 74139 CNT4BUDA ENC10TO4
Contextual Info: VANTIS Soft Macro Reference Manual Basic Function Macros 1999 Vantis Application Center 1 TABLE OF CONTENTS Macro Name CNT4BUDA CNT4BUL CNT4DUDA CNT4DUL COMP4MAG COMP8EQ DEC2TO4 DEC3TO8 DEC4T10 DEC4T10N DEC4TO16 DFF8AR ENC10TO4 ENC8TO3 FADD1C FADD2C FADD4C

744040

Abstract: scx6206 74589 744020 Flip-Flop 7471 744017 744017 counter sn 74373 scx6218 74395
Contextual Info: July 1985 SCX m icroC M O S G ate A rray Fam ily A pplication G uide TABLE OF CONTENTS 1.0 General Description . 2 2.0 Product Features. 2 Enhanced Product Features. . 2

SN74298

Abstract: 54175 IC 74157 7429 ttl
Contextual Info: SN54298, SN54LS298, SN74298, SN74LS298 QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE MARCH 1974 - REVISED M AR C H 19B 8 S N 54298, SN 54LS298 . . . J OR W PACKAGE S N 7429 8 . . . N PACKAGE SN74LS298 . . . D OR N PACKAGE Selects One of Two 4-Bit Data Sources

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Contextual Info: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte­ grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p­

ALU IC 74381

Abstract: encoder IC 74147 16CUDSLR 74139 truth table alu 74382 truth table for 7446 from ic 7447 truth table IC 74373 truth table pin diagram of ic 74190 truth table for ic 74138
Contextual Info: PLDS-HPS, PLS-HPS, PLS-OS & PLS-ES A N & * r a \ MAX+PLUS II Programmable Logic Development System & Software Data Sheet S eptem ber 1991, ver. 1 U M A X + P L U S II is the single, u nified d e velo p m e n t system for A lte ra 's C lassic, M A X 5000, M A X 7000, and S T G E P L D s .

16CUDSLR

Abstract: 7474 D flip flop free alu 74382 counter schematic diagram 74161 sn 74373 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151 IC 74373 truth table
Contextual Info: PLDS-MAX & PLS-MAX M MAX+PLUS Program mable Logic Developm ent System & Software M Data Sheet September 1991, ver. 1 □ □ □ □ □ □ □ □ □ S o ftw a re su p p o rt for M A X 5000 M u ltip le A rray M atriX E PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Contextual Info: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte­ grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

priority encoder 74148

Abstract: priority encoder 74147 shift register 7495 msm7200 MSM7000 alu 74381 msm7500 MSM72000 74150 demultiplexer multiplexers 74 LS 150
Contextual Info: • G EN ER A L DESCRIPTION T h e M S M 7 0 0 0 0 series is the gate array L S I based on the master siice m ethod using the high perform ance silicon gate H C M O S process w ith the dual-layer metal structure. T h is series has the features to easily realize fu n c tio n s-o f the sch m itt trigger, crystal/

lm294oct

Abstract: d71054c D71055C lm294oct-12 74c928 7486 XOR GATE interfacing ADC 0808 with 8086 microprocessor 555 7490 7447 7 segment LED display Motorola 74LS76 NEC D71055C
Contextual Info: Integrated Circuits 74LS Series Featuring better performance than standard 7400 series devices, the 74LS series also uses about 1/5th the power. Part# Pins Description 74LS00 74LS01 74LS02 74LS03 74LS04 74LS05 74LS06 74LS07 74LS08 74LS09 74LS10 74LS11 74LS12

AMD K6

Abstract: 74147 decimal to binary encoder
Contextual Info: a Preliminary Am3020/3030/3042/3064/3090 Advanced Micro Devices Am3000 Series Family of Programmable Gate Arrays DISTINCTIVE CHARACTERISTICS • Second generation user-programmable gate array ■ Flexible array architecture ■ High performance - 50 ,7 0 ,1 0 0 MHz commercial products

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 jk flip flop to d flip flop conversion alu 74381 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
Contextual Info: • G E N E R A L D ESCRIPTIO N T h e M S M 7 0 H 0 0 0 series is the gate array L S I based on the m aster slice m ethod using the high perfo rm an ce silico n gate 2 m icro n H C M O S process w ith the d u al-layer m etal s tru ctu re . T h is series has the featu res to ea sily realize fu n c tio n s o f the sch m itt trig ger, c ry s ta l/

74194 ring counter

Abstract: grid tie inverter schematic diagram 74299 universal shift register CI 74241 DN 74352 grid tie inverter schematics 7483 parallel adder pin diagram multiplexor 74153 multiplexor 74151 grid tie inverters circuit diagrams
Contextual Info: H Preliminary Am3020/3030/3042/3064/3090 Advanced Micro Devices Am3000 Series Family of Programmable Gate Arrays DISTINCTIVE CHARACTERISTICS • Second generation user-programmable gate array ■ Flexible array architecture ■ High performance - 50, 70,100 MHz commercial products