64WORDS Search Results

MSM6252RS

Abstract: M6252 F3341 MSM6252
Contextual Info: J2W0034-27-X2 作成：1998年 1月 MSM6252 l 前回作成：1996年 7月 ¡ 電子デバイス MSM6252 64wordsx4Bit FIFO n 概要 MSM6252は，シリコンゲートCMOSを用いた64words×4 bits First In First Out Memoryで，Fairchild 3341 MOS FIFOとはコンパチブルでデータの入力 Shift In は非同期動作が可能です。またビットおよ

KSC5601

Abstract: D8A1 KS0040 d6a1 16f7 1B60 H124 128X8 16X16 8X16
Contextual Info: KS0040 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD APRIL. 1999. KS0040 65COM/132SEG DRIVER & CONTROLLER FOR STN LCD KS0040 Specification Revision History Version 0.0 1.0 1.1 2 Content Original 1 Changed function MPU interface pin & method are changed.

Contextual Info: IDT49C402 IDT49C402A IDT49C402B 16-BIT CMOS MICROPROCESSOR SLICE Integrated Device Technology, Inc. FEATURES: • Functionally equivalent to four 2901s and one 2902 • IDT49C402B is 60% faster than four 2901 Cs and one 2902A • Expanded tw o-address architecture with independent, si­

IDT49C402A

Abstract: idt49C402
Contextual Info: 16-BIT CM OS M ICRO PRO CESSO R SLICE FEATURES: IDT49C402 IDT49C402A IDT49C402B The IDT49C402S include all of the normal functions associated with standard 2901 bit-slice operation: a a 3-bit instruction field lo, H, |2 ) which controls the source operand

404608H

Contextual Info: H D404608/H D4074608 D escription Type of P ro d u cts T he MCU is a m icro co m p u ter u n it w h ic h h a s p o w erfu l a n d efficien t a rc h ite c tu re of th e HMCS400 family. T he MCU in c o rp o ra te s a h ig h -p recisio n d u a l to n e m u lti-fre q u e n c y

74F433

Abstract: 74F433SPC B255 N24C S9423
Contextual Info: Revised August 1999 74F433 First-In First-Out FIFO Buffer Memory General Description Features The 74F433 is an expandable fall-through type high-speed First-In First-Out (FIFO) Buffer Memory that is optimized for high-speed disk or tape controller and communication

tk5551

Contextual Info: Features • High Performance, Low Power Atmel AVR 8-bit Microcontroller • Advanced RISC Architecture – 123 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories

Contextual Info: New Data File N um ber 2122 CD54/74HC7030 CD54/74HCT7030 64-Word x 9-Bit FIFO Register; 3-State Type Features: 92CS-42860 FUNCTIONAL DIAGRAM • S ynchronou s o r asynchronous o peration ■ 3-state ou tputs standard ■ M a ster-reset in p u ts to clear data

Contextual Info: S71WSxxxJ based MCPs Stacked Multi-Chip Product MCP 128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM PRELIMINARY Distinctive Characteristics MCP Features „ „ Power supply voltage of 1.7 to 1.95V

S29WS128J-MCP

Abstract: S29WS128J S29WS-J S29WS064J
Contextual Info: S29WS-J 128/64 Megabit 8/4 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet S29WS-J Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information,

RTS5158

Abstract: northbridge G41 se u10i layout GM965 28K1 IC NS0013 sla5t bga676 rtl8010 C1087
Contextual Info: A B C D E X'TAL 14.318MHz Merom Processor System Power Rail Management Dual-Core CLOCK GEN ICS9LPR358AGLFT uFCPGA 478 2 3,4 FSB (667/800 MHz) FSB 4 GM965/PM965 ATI M74M USB 1 LVDS ＊V ＊VS HIGH HIGH ON ON ON ON S3 (Suspend to RAM) LOW HIGH HIGH HIGH ON

SPARTAN-3A DSP 3400A

Abstract: AD7180 schematic diagram vga to rca CH7301 SPARTAN camera link interface of camera with virtex 5 fpga for image image sensor micron 9V022 block diagram images of lcd display 16x2 MT9V022 i2c
Contextual Info: Spartan-3A DSP FPGA FPGA Starter Video Video Kit Starter Kit User Guide [Guide Subtitle] [optional] UG456 v2.0 November 17, 2008 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development

F433

Contextual Info: 433 54F/74F433 First-In First-Out FIFO Buffer Memory Connection Diagrams Donription J n y P u t o f i an expandable fall-through type high-speed first-in first-o u t * I F O )Jm ijm J*WLory tha t is op tim ize d fo r high-speed d isk o r tape c o n trc M e y iy K m a fc u n ic a tio n b u ffe r ap plicatio ns. It is organized as 64

trw1030

Abstract: AC723
Contextual Info: AC723 • ACT723 54AC/74AC723 • 54ACT/74ACT723 64 x 9 First-In, First-O ut M em ory Description Connection Diagrams The ’AC/’ACT723 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data

Contextual Info: New Data File Number 2122 CD54/74HC7030 CD54/74HCT7030 64-Word x 9-Bit FIFO Register; 3-State Type Features: 92 CS - -»2860 FUNCTIONAL DIAGRAM • Syn chronous or asynchronous operation • 3-state outputs standard ■ M aster-reset inputs to clear data

Contextual Info: S E M IC O N D U C T O R tm 74ACT2708 64 x 9 First-In, First-Out Memory General Description Features The ACT2708 is an expandable first-in, first-out memory or­ ganized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed

HD404808H

Abstract: HD404808FS HD4074808FS HD404808 DS 09 1007 1012 D4 S050S hd40l4808fs ic hd4074808 DS 09 1007 1038 D4 HD4074808H
Contextual Info: H D404808/H D4074808/ H D40L4808/H D407L4808 D escription • T h e M C U is a 4 -b it sin g le c h ip H M C S 4 0 0 s e r ie s m ic ro c o m p u te r p ro v id in g h ig h p ro g ro m p ro d u ctiv ity . I t in c o rp o ra te s la r g e siz e m e m o ry , L C D d r iv e r / c o n t r o lle r , v o lt a g e

hr 433C

Contextual Info: &N a t i o n a l Cd <4 Semiconductor 74F433 First-In First-Out FIFO Buffer Memory General Description Features The ’F433 is an expandable fall-through type high-speed first-in first-out (FIFO) buffer memory that is optimized for high-speed disk or tape controller and communication buffer

cy 4902

Contextual Info: ^ STRUCTURE O P R O D U C T NAME O P A R T NUM BER O O U T U N E DIMENSION O B L O C K DIAGRAM ^ FU N C T IO N OFEATURES Silicon Monolithic Integrated Circuit 64 x 16 bit Electrically Erasable Programmable ROM B R 9 3 L 4 6 / F / R F / F J / R F J / F V / R F V / R F V M -W

SA266-4

Abstract: S71WS128JB0 S71WS128JC0 S71WS256JC0 S71WS-J FBGA 12x12 TRAY
Contextual Info: S71WS-J Based MCPs Stacked Multi-Chip Product MCP Package-on-Package (PoP) 128/64 Megabit (8M/4M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with CellularRAM ADVANCE INFORMATION Data Sheet Notice to Readers: The Advance Information status indicates that this

Contextual Info: Preliminary KS0040 65COM/132SEG DRIVER & CONTROLLER FOR STN LCD 1. INTRODUCTION DOT MATRIX LCD CONTROLLER & DRIVER KS0040 is a dot-Matrix liquid crystal display LCD controller and driver LSI that displays asian language characters like Chinese, Japanese or Korean.

16MHZ

Abstract: 32768HZ SNL310 Sound of silence piano sheets 0c002 md4t snl310 programming guide
Contextual Info: SNL310 Application Note Volume I = 1. Play Speech 2/2.8/3.6/8Kbps . 21 Play Voice (10~29Kbps) . 22 Play PCM . 23

DIODE HF 20

Abstract: 74ACT2708 74ACT2708PC N28B
Contextual Info: Revised January 1999 74ACT2708 64 x 9 First-In, First-Out Memory General Description Features The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed

APM4546

Abstract: BR93L46RFVM-W BR93L46FJ-W BR93L46FV-W BR93L46F-W BR93L46RFJ-W BR93L46RFV-W BR93L46RF-W BR93L46-W TA40qC
Contextual Info: Silicon Monolithic Integrated Circuit 64 x 16 bit Electrically Erasable Programmable ROM B R 9 3 L 4 6 /F /R F /F J /R F J /F V /R F V /R F V M -W Fig. - 1 Plastic Mold Fig. - 2 General purpose •64words x 16 bit organization 1kbit serial EEPROM ■Wide operating supply voltage ranged.8 ~ 5.5V)