54LS26 Search Results

Contextual Info: a National Semiconductor 54LS266/DM74LS266 Quad 2-Input Exclusive-NOR Gate with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic exclusive-OR function. Outputs are open collector. Connection Diagram

Contextual Info: g M ilita ry 54L S 26 MOTOROLA Quad 2-In p u t In verter/B u ffer Driver ELECTRICALLY TESTED PER: MIL-M-38510/32102 M P 0 l/ I I W LOGIC DIAGRAM VCC râ B4 A4 Y4 B3 A3 Y3 ra ra nil Roi nn fsi AVAILABLE AS: 1) JAN: JM38510/32102BXA 2) SMD: 7602001 3)883: 54LS26/BXAJC

SM74LS08

Abstract: 74ls183 LS261 SN74LSOO wallace tree Binary Multipliers SN74LS261 wallace tree multiplier "Binary Multipliers" SN54LS261
Contextual Info: 54LS261, SN74LS261 2-BIT BY 4-BIT P A R A L L E L BINARY M ULTIPLIERS SD LS150 MARCH 197 4 - Fast Multiplication . . , 5-B it Product in 26 ns Typ SN 54LS261 . . J OR W SN 74LS261 REVISED M A R C H 1 9 8 8 PACKAGE . . . D OR N PACKAGE Power Dissipation . . . 110 mW Typical

Contextual Info: LS26 National Semiconductor 54LS26/DM74LS26 Quad 2-Input NAND Gates with High Voltage Open-Collector Outputs Pull-Up Resistor Equations General Description Vp Min - Vqh This device contains four independent gates each of which performs the logic NAND function. The open-collector out­

54LS

Abstract: 54LS26DMQB 54LS26FMQB DM74LS26M DM74LS26N J14A M14A N14A W14B
Contextual Info: NATIONAL SEMICOND {LOGIC* 31E D bSG HES DObTTtiS 3 I 7 ^ 4 3 - /6 - 0 0 54LS26/DM74LS26 Quad 2-lnput NAND Gates with High Voltage Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains four independent gates each of which

54LS260

Abstract: 54LS260DMQB 54LS260FMQB 54LS260LMQB DM74LS260M DM74LS260N E20A J14A M14A N14A
Contextual Info: £ 2 National Semiconductor 54LS260/DM74LS260 Dual 5-Input NOR Gate General Description This device contains two individual five input gates, each of which perform the logic NOR function. Connection Diagram Dual-ln-Line Package TL/F/9824-1 Order Number 54LS260DMQB, 54LS260FMQB,

Contextual Info: g MOTOROLA M ilita ry 54L S 2 6 6 Quad 2-In p ut E xclusive NOR G ate kSÌÌÈSÉ MPO ELECTRICALLY TESTED PER: MIL-M-38510/30303 LOGIC DIAGRAM M fi^ llil pi] |T] [iol [T1 |T| V cc B4 A4 Y4 Y3 B3 A3 W AVAILABLE AS: 1) JAN: JM38510/30303BXA 2) SMD: N/A 3)883: 54LS266/BXAJC

Contextual Info: a National Semiconductor 54LS260/DM74LS260 Dual 5-Input NOR Gate General Description This device contains two individual five input gates, each of which perform the logic NOR function. Connection Diagram Dual-ln-Llne Package TL/F/9824-1 Order Number 54LS260DMQB, 54LS260FMQB,

Contextual Info: MOTOROLA M ilitary 54LS26 Q u ad 2-Input Inverter/Buffer D rive r ELECTRICALLY TESTED PER: MIL-M-38510/32102 A VAILABLE A S: LOGIC DIAGRAM Vcc i«l 64 A4 Y4 f°1 fiil R 83 [ il A3 Y3 1 JA N : JM38510/32102BXA 2) S M D : 7602001/XA 3) 883C: 54LS26/BXAJC fil iïl

Contextual Info: ^ MOTOROLA M ilita ry 54L S 26 Quad 2-In p u t In verter/B u ffer D river <( ELECTRICALLY TESTED PER: MIL-M-38510/32102 K P 0 llllll' LOGIC DIAGRAM Vcc 64 A4 V4 B3 A3 Y3 AVAILABLE AS: 1) JAN: JM 38510/32102BXA 2) SMD: 7602001 3)8 8 3 : 54LS26/BXAJC X = CASE OUTLINE AS FOLLOWS:

Contextual Info: LS260 NATIONAL SEflICOND -CLOGIC} 31E D m b S G H E S GQ7QQ3G 5 National Semiconductor 54LS260/DM74LS260 Dual 5-Input NOR Gate General Description This device contains two individual five input gates, each of which perform the logic N O R function. Connection Diagram

74LS266M

Contextual Info: TYPES 54LS266, SN74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COLLECTORS OUTPUTS D E C E M B E R 19 7 2 - H E V IS E D D EC EM BE R 1983 • Can Be Used as a 4-Bit Digital Comparator SN 54LS266 I OR W PACKAG E S N 7 4 L S 2 6 6 . . . D, J OR N P A C K A G E

Contextual Info: SN5426, 54LS26, SN7426, SN74LS26 . QUADRUPLE 2 INPUT HIGH VOLTAGE INTERFACE POSITIVE-NAND GATES DECEMBER 19 B 3 - REVISED M AR C H 1988 SN 5426 SN 54LS26 . S N 7426 SN 74LS26 . F o r D riv in g L o w -T h re s h o ld -V o lta g e M O S In p u ts . . . J PACKAGE

Contextual Info: MOTOROLA Military 54LS266 Quad 2 -In p u t Exclusive NOR G ate ELECTRICALLY TESTED PER: MIL-M-38510/30303 LOGIC DIAGRAM V X R B4 R A4 U Y3 R R W B3 R AVAILABLE AS: A3 [il 1 JAN: JM 38510/30303BXA 2) SMD: * 3) 883C: 54LS266/BXAJC X = CASE OUTLINE AS FOLLOWS:

Contextual Info: 54LS261, SN74LS261 2 BIT BY 4-BIT PARALLEL BINARY MULTIPLIERS MARCH 1974 5N 54LS261 SN74LS261 Fast Multiplication . . . 5-Bit Product in 26 ns Typ Power Dissipation . . . 110 mW Typical . . J OR W P A C K A G E . . D OR N P A C K A G E TO P V IE W Latch Outputs for Synchronous Operation

Contextual Info: MOTOROLA M ilita ry 54L S 2 6 6 Quad 2-In pu t Exclusive NOR G ate ELECTRICALLY TESTED PER: MIL-M-38510/30303 MPO unw LOGIC DIAGRAM Vcc B4 A4 Y3 B3 A3 AVAILABLE AS: ? A1 Y4 1 JAN: JM38510/30303BXA 2) SMD: N/A 3)883: 54LS266/BXAJC <51 B1 Y1 Y2 A2 B2 X = CASE OUTLINE AS FOLLOWS:

diagram ta 306

Abstract: 54LS266 54LS266DMQB 54LS266FMQB DM74LS266M DM74LS266N J14A M14A N14A W14B
Contextual Info: y n National ÆjàSemiconductor 54LS266/DM74LS266 Quad 2-Input Exclusive-NOR Gate with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic exclusrve-OR function. Outputs are open collector.

Contextual Info: TYPES SN74LS26, 54LS26 QUADRUPLE 2-INPUT HIGH-VOLTAGE INTERFACE POSITIVE-NAND GATES R E V IS E D D E C E M B E R 1983 • For Driving Low-Threshold-Voltage M O S Inputs 8N 54LS26. J PA CKAG E SN 74LS26. D OR N PA CKAG E TO P VIEW * Package Options Include Standard Plastic

74LS266M

Abstract: LS266 74L826 74LS266
Contextual Info: TYPES SN54LS286, SN74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COUECTOR OUTPUTS TTL MSI B U L L E T IN NO. D L-S 7611843, D E C E M B E R 1 9 7 2 - R E V IS E O O C T O B E R 1B7S S N 6 4LS 266 . . . J O R W P A C K A G E SN 74LS266. . . J OR N P A C K A S E

74LS266PC

Abstract: 54LS266FM 54LS266DM 74LS266DC 74LS266FC
Contextual Info: 266 C O N N E C T IO N D IA G R A M P IN O U T A 54LS /74LS 266 QUAD 2-IN P U T EXCLUSIVE-NOR GATE W ith O p e n -C o lle c to r O utputs 4 O R D E R IN G C O D E : See S e c tio n 9 PIN PKG S OUT C O M M E R C IA L G R AD E M IL IT A R Y G R AD E V c c = + 5.0 V ±5%,

Contextual Info: 54LS261, SN74LS261 2-BIT BY 4-BIT PARALLEL BINARY MULTIPLIERS MARCH 1974 - REVISED MARCH 1988 Fast M ultiplication . . . 5-Bit Product in 26 ns Typ S N 5 4 L S 2 6 1 . . . J OR W P AC KA G E S N 7 4 L S 2 6 1 . . . D OR N P AC K A G E Power Dissipation . . . 110 mW Typical

ic 74LS266

Contextual Info: 54LS266, SN74LS266 QUADRUPLE 2-INPUT EXCLUSIVE NOR GATES WITH OPEN COLLECTORS OUTPUTS DECEMBER 1972 - REVISED MARCH 1988 • Can Be Used as a 4-Bit Digital Comparator SN 5 4 L S 2 6 6 . . . J OR W PACKAG E SN 7 4LS2 66 . . . D OR N PACKAG E Input Clamping Diodes Simplify System

74LS260N

Abstract: 54LS260J
Contextual Info: S E M IC O N D U C T O R tm DM74LS260 Dual 5-Input NOR Gate General Description This device contains tw o individual five input gates, each of w hich perform the logic N OR function. Connection Diagram D ual-ln-Line Package 14 2 T 13 r 5 * JO 6 _ | 1_ 9-

Contextual Info: 260 CONNECTION DIAGRAM PINOUT A 54S/74S260 6>/0^c+o i/54LS/74LS260 O H ö q q DUAL 5-INPUT NOR GATE E ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%. T a = 0° C to +70° C V cc = + 5 .0 V ±10%, T a = -55° C to +125° C