38VCC Search Results

TXC10 M 60

Abstract: 10BASE2 10BASE5 93LC46B FPT-144P-M08 MB86961A MB86974 NM93C46
Contextual Info: PAUSE FLOW CONTROL 10Mb/s-/100Mb/s Ethernet Controller MB86974 Package • 144-pin, plastic QFP • FPT-144P-M08 Description The Fujitsu MB86974 is a high-quality Ethernet controller that offers many benefits and advantages to its users. The controller operates at either 100-Mbit/s or 10-Mbit/s, and

rx2 99

Abstract: 93c46l 93c46li 16C550 AD29 AD30 XR17V258 bu 515 144LQFP 16550
Contextual Info: XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT AUGUST 2010 REV. 1.0.2 GENERAL DESCRIPTION The XR17V2581 V258 is a single chip 8-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Receiver and Transmitter)

Contextual Info: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Introduction • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI

54SX32

Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Contextual Info: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)

TCI D2S

Abstract: TCI D2S f BRA16 128-Byte CSR19 M1FD STMicroelectronics BET
Contextual Info: STE10/100 PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY PRODUCT PREVIEW 1.0 DESCRIPTION The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application. It was designed with advanced CMOS technology to

intel 82596

Abstract: 82559 Reference Manual 82559 LF8200A Three-Five 1229H 82557 user manual 82557 TCP 8118
Contextual Info: 82559 Fast Ethernet* Multifunction PCI/ CardBus Controller Networking Silicon Datasheet Product Features • ■ Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface

PQFP128

Abstract: 93C46 PC99 ci 9410 HB626-1 IBM REV 2.8 TCI D2S
Contextual Info: STE10/100A PCI 10/100 Ethernet controller with integrated PHY 3.3V Features • IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant ■ Support for IEEE802.3x flow control ■ IEEE802.3u auto-negotiation support for 10BASE-T and 100BASE-TX ■ PCI bus interface rev. 2.2 compliant

AD27

Abstract: AD29 V320USC V320USC-75 AD1485
Contextual Info: DS-UC01-0102.fm Page 1 Wednesday, June 30, 1999 7:30 PM Datasheet V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus

TDA 7378

Abstract: TDA 7822 block diagram baugh-wooley multiplier tda 12062 equivalent for tda 4858 ic free transistor equivalent book STD-80 4856 a 14 PIN DIP W908 LSI CMOS Technology
Contextual Info: D • A • T • A • B • O • O • K STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library April 1997 V SAMSUNG SAMSUNG ASIC STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library Data Book  1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior

Contextual Info: v3.0 SX-A Family FPGAs Leading-Edge P erfo rm an c e • 250 MHz System Performance • 3.8ns Clock-to-Out Pad-to-Pad • 350 MHz Internal Performance S p ec ific atio n s • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins

rdl 117-a

Abstract: pa-1000b
Contextual Info: A d v a n c e d v O .7 ? TM P r o A S IC ^ F la s h F a m ily F P G A s High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization I/O Schmitt-Trigger Option on Every Input Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate

54sx08

Abstract: THERMAL Fuse m20 tf 115 c
Contextual Info: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up

Contextual Info: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew

Contextual Info: 82551IT Fast Ethernet PCI Controller Networking Silicon - 82551IT Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 checksum offload — Received checksum verification Quality of Service QoS — Multiple priority transmit queues

82551it

Contextual Info: 82551QM Fast Ethernet Multifunction PCI/CardBus Controller Networking Silicon - 82551QM Datasheet Product Features • ■ ■ ■ ■ ■ ■ Enhanced IP Protocol Support — TCP, UDP, IPv4 Checksum Offload — Received Checksum Verification Quality of Service QoS

application notes of TF 513

Abstract: PHSOSCK17 PHSOSCK27 STD130
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

CL 2181

Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Contextual Info: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)

TDA 9361 PS

Abstract: tda 2974 LD5Q ci 8602 gn block diagram TDA 2265 5.1 AUDIO AMP TDA 2030 TDA 7877 TDA 0200 circuit TDA 9594 TDA 2088
Contextual Info: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

OB33LN

Abstract: ProASICPLUS Flash Family FPGAs v3.3
Contextual Info: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

Contextual Info: v5.0 ProASICPLUS TM Flash Family FPGAs Features and Benefits • High Capacity High Performance Routing Hierarchy Commercial and Industrial • • • • • • • 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os

schematic diagram online UPS for high frequency

Abstract: ag19
Contextual Info: v3.3 ProASICPLUS TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process

APA750

Abstract: GL25 4kx8 sram
Contextual Info: v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits • • High Capacity I/O • • • • • 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology • • • • 0.22µ 4LM Flash-based CMOS Process