37417SL Search Results

MB86686A

Contextual Info: MB86683B Edition 1.0 1. OVERVIEW The NTC is a full duplex device which can be used to provide broadband termination functions in a variety of applications. Its primary use is for terminating the user or network ends of a user-network interface based on ITU-T,

dmr 42

Contextual Info: April 1994 Edition 1.0 FUJITSU DATA SHEET MB86604A SCSI-11 PROTOCOL CONTROLLER WITH SIN G LE-EN D ED DRIVER/RECEIVER DESCRIPTION The Fujitsu MB86604A is a single-ended transmission type SCSI—II Protocol Controller SPC with a single-ended driver/receiver. The MB86604A facilitates interface control

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET D S 0 4 -2 9 1 0 2 -2 E BIDIRECTIONAL MOTOR DRIVER MB3763H • DESCRIPTION Fujitsu’s MB3763H Motor Driver with forward/reverse control capability, is used in applications such as the frontloading mechanism in video cassette recorder or the auto-reverse tape deck, driven by a TTL signal. The

Contextual Info: cP DS04-13103-5E FUJITSU DATA SHEET LINEAR IC 6-CHANNEL 8-BIT A/D CONVERTER MB4053 6-CHANNEL 8-BIT A/D CONVERTER SUBSYSTEM The Fujitsu MB4053 is 6-channel, 8-bit, single-slope A/D converter subsystem designed to be used in a microprocessor based data control system. This device provides the analog functions

814260

Abstract: PJ 1269
Contextual Info: November 1993 Edition 2.0 FUJITSU DATA SHEET M B 8 14260-60/-70/-80 CM O S 2 5 6 K X 16 BIT FAST PAGE M O D E DYNAMIC RAM CMOS 262,144 x 16 bit Fast Page Mode Dynamic RAM The Fujitsu MB814260 is a fully decoded CMOS Dynamic RAM DRAM that oontains 4,194,304

Contextual Info: <£ DS04-21340-1E DATA SHEET FUJITSU ASSP Single Serial Input PLL Frequency Synthesizer On-Chip 1.2 GHz Prescaler MB15E03 • DESCRIPTION The Fujitsu MB15E03 is a serial input Phase Locked Loop PLL frequency synthesizer with a 1.2 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.

Contextual Info: -P R E L IM IN A R Y October 1995 Edition 1.1 = FUJITSU PRODUCT PROFILE SHEET MB 8 116165 A- 60/-70 CMOS 1M X 16BIT HYPER PAGE M O D E DYNAMIC RAM CMOS 1,048,576 x 16BIT Hyper Page Mode Dynamic RAM The Fujitsu MB8116165A is a fully decoded CMOS Dynamic RAM DRAM that contains

GG41

Contextual Info: April 1993 Edition 2.1 FUJITSU DATA S H E E T M B 8 1 8 2 5 1 -70/-80 2097,152 Bits 262,144 x 8 Bits Multi-port CMOS Dynamic RAM The Fujitsu MB818251 is a fully decoded dual port CMOS Dynamic RAM (DRAM) organized as 262,144 words by 8 bits dynamic RAM port and 512 words by 8 bits serial

Contextual Info: - PRE LIM IN AR Y- April 1996 Edition 2.2 FUJITSU PRO DUCT PROFILE SHEET M B 8 14405C-60/-70 CMOS 1 M X 4 BIT HYPER PAGE MODE DRAM CMOS 1,048,576 x 4 bit Hyper Page Mode Dynamic RAM The Fujitsu MB814405C is a fully decoded CMOS Dynamic RAM DRAM that contains 4,194,304

Contextual Info: FUJITSU S EM ICO NDUCTO R DATA SHEET ASSP Communication Control Data Link Controller DLC MB89374 • DESCRIPTION The MB89374 Data Link Controller (DLC) controls transfer of serial data in accordance with Bit Oriented Protocol (BOP). It supports protocols such as High level Data Link Control (HDLC) (the BOP mode) and Serial Data

MB88341-P

Abstract: MB88401 MB88342 r2r resistor ladder MB88342-PF DIP-20P-M02 MB88341 MB88342-P
Contextual Info: cP DS04-13504-6E - FUJITSU DATA SHEET LINEAR 1C R-2R TYPE 8-BIT D/A CONVERTER MB88341/MB88342 DESCRIPTION M B88341-P M B88342-P PLASTIC DIP D IP -20P -M 02 PLASTIC DIP (D IP -16P -M 04) The Fujitsu MB88341 and MB88342 are R-2R type 8-b it resolution digital-to-analog

D1186

Abstract: MB89251 REM BB2
Contextual Info: MB86940 FUJITSU 930 Series Companion Chip DATASHEET FEA TU RES AUGUST 1994 _ • Integrated Interrupt Request Controller, Timer, and Serial D ata Transmitter/Receiver • 930 Series processor interface • 40 MHz operation

Contextual Info: DS07-12536-2E • OUTLINE The MB89940 series is specially designed for automotive instrumentation applications. It features a combination of two PWM pulse generators and four high-drive-current outputs for controlling a stepping motor. It also contains two analog inputs, two PWM pulse generators and 10-digit LCD controller/driver for various sensor/indicator

Contextual Info: M B86960 F ilim i! NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATASHEET A P R IL I 9 9 3 FEA TU R ES • High-performance packet buffer architecture pipe­ lines data for highest throughput • 20 Mbyte/second datatransferrate to/from thesystem

LBR 84

Contextual Info: Edition 2.0 1. MB86687 OVERVIEW The ALC simultaneously supports autonomous segmentation and reassembly of user data packets on up to 1024 virtual circuits VCs . User data packets are transferred to and from shared data structure memory using a high speed intelligent DMA

MB90089

Abstract: MB90089-PF character generator kanji rgb
Contextual Info: Él FUJITSU SEMICONDUCTOR DATA SHEET f DS04-28821-1E ASSP ON-SCREEN DISPLAY CONTROLLER MB90089 DESCRIPTION The MB90089 CMOS On-screen Display Controller OSDC is a peripheral LSI that displays 288 alphanumeric characters (24 rows x 12 lines) and figures on TV screen by a microcontroller. Since the MB90089 contains a

Contextual Info: ASSP SWITCHING REGULATOR CONTROLLER MB3778 • DESCRIPTION The MB3778 is a dual switching regulator control 1C. It has a basic circuit that controls PWM system switching regulator power for two channels. Complete synchronization is achieved by using the same oscillator output.

Contextual Info: PRELIMINARY- October 1995 Edition 1.0 • - .■ = FUJITSU P R O D U C T P R O F IL E S H E E T MB8 118165A-60/-70 CMOS 1M X 16BIT HYPER PAGE M O D E DYNAMIC RAM CMOS 1,048,576 x 16BIT Hyper Page Mode Dynamic RAM The Fujitsu MB8118165A is a fully decoded CMOS Dynamic RAM DRAM that contains

a9aa fpt

Contextual Info: FLASH MEMORY OÍOS 4 c y M nfl v / o \ B I T lb M \¿ M X o/ d i I MBM29F017 -90/-12 • DISTINCTIVE CHARACTERISTICS Single 5.0 V read, write, and erase .s». Minimizes system level power requirements Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Ftesh

Contextual Info: M B86964 FUJITSU ETHERNET CONTROLLER WITH 10BASE-T TRANSCEIVER PRELIMINARY DATA SHEET DECEMBER 1993 M B 8 6 9 6 4 ’s transm it buffer is p ro g ram m a b le as a single i FEATURES F ully co m p lian t w ith IS O /A N S I/IE E E 8802-3 sp ecific a­ tions

Contextual Info: Feburuary 1993 Edition 1.0 HATA S H F F T MB89413 OUTLINE FONT GENERATOR 2 OFG\ I DESCRIPTION The OFGII is a large-scale Integrated circuit (LSI) that draws an outline defined by lines and curves (cubic Bezier curve and cubic B-spline curve) and rasterizes an intemally-fliled

S2Z3

Abstract: FAR-F6CH-1G3590-S2Z3 890MHZ
Contextual Info: ASSP Mobile Communication Systems Piezoelectric SAW BPF 700 to 1700 MHz F5/F6 Series (S2 type) Soft SAW • DESCRIPTION The S2 type of SAW bandpass filters are named “Soft SAW” because of their performance. The S2 type filters have low insertion loss in passband and are housed in a small surface mount package. Moreover,

412F6

Abstract: 1 to 3 GHz bandpass filter wide band 2.4 GHz Bandpass Filters marking IRH 2 SB 1785 74288 DS04-23110-2E
Contextual Info: DS04-23110-2E ASSP for Mobile Communication Systems Piezoelectric SAW BPF 1000 to 2500 MHz F6 Series (L2 Type) • DESCRIPTION The F6 series of SAW bandpass filters apply to the frequency range 1000 to 2500 MHz. The SAW filters are fabricated on a lithium tantalate (LiTaCh) substrate, producing filters with a wide frequency

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-20824-2E FLASH MEMORY CMOS 4 M 5 1 2 K X 8 MBM29LV004T/MBM29LV004B • FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands * * * •