16BIT Search Results

Contextual Info: TC74LCX16373AFT LOW-VOLTAGE 16-BIT D-TYPE LATCH WITH 5V TOLERANT INPUTS A N D OUTPUTS T h e TC74LCX16373AFT is a high p erform an ce C M O S 16bit D-TVPE LATCH. Designed fo r use in 3.3 V o lt systems, it achieves high speed o p e ra tio n w h ile m ain tain in g the

2A334

Abstract: 1A739
Contextual Info: IN T EG RA T ED TO SHIBA CIRCUIT TECHNICAL TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT TC74LCX16646FT DATA SILICON MONOLITHIC TENTATIVE DATA LOW VOLTAGE 16-BIT BUS TRANSCEIVER I REGISTER WITH 5V TOLERANT INPUTS AND OUTPUTS The TC74LCX16646FT is a high performance CMOS 16bit

K4S64163LF

Contextual Info: K4S64163LF-G A G/S CMOS SDRAM 4Mx16 Mobile SDRAM 52CSP (VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR) Revision 1.4 December 2002 Rev. 1.4 Dec. 2002 K4S64163LF-G(A)G/S CMOS SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 52CSP FEATURES GENERAL DESCRIPTION • 2.5V power supply.

K4E641612C

Abstract: K4E641612C-T K4E661612C K4E661612C-T
Contextual Info: K4E661612C,K4E641612C CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle 4K Ref. or 8K Ref. , access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden

K4S641632F-TC75

Abstract: K4S641632F
Contextual Info: K4S641632F CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 May. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 May. 2003 K4S641632F CMOS SDRAM Revision History Revision 0.0 June, 2001

K4M51163LE

Contextual Info: K4M51163LE - Y P C/L/F Mobile-SDRAM 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 2.5V power supply. The K4M51163LE is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the

K4M28163LF

Contextual Info: K4M28163LF - R B E/N/S/C/L/R Mobile-SDRAM 2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 2.5V power supply. The K4M28163LF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits,

K4S641633F

Contextual Info: K4S641633F-G A L/N/P CMOS SDRAM 4Mx16 Mobile SDRAM 52CSP (VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V) Revision 1.4 December 2002 Rev. 1.4 Dec. 2002 K4S641633F-G(A)L/N/P CMOS SDRAM 1M x 16Bit x 4 Banks SDRAM in 52CSP FEATURES GENERAL DESCRIPTION • 3.0V power supply.

K4M56163PE-R

Contextual Info: K4M56163PE - R B G/F Mobile-SDRAM 4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 1.8V power supply. The K4M56163PE is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design make a device controlled precisely

S8S3122X16

Abstract: S8S3122X16-TCR1 S8S3122X16-TCR2
Contextual Info: S8S3122X16 CMOS SDRAM 256K x 16 SDRAM 128K x 16bit x 2 Banks Synchronous DRAM LVTTL Version 0.0 Sep 2001 Samsung Electronics reserves the right to change products or specification without notice. Ver 0.0 Sep. '01 S8S3122X16 CMOS SDRAM Revision History Version 0.0 Sep. 2001

K4S64163LH

Contextual Info: K4S64163LH - R B E/N/G/C/L/F Mobile-SDRAM 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • 2.5V power supply. The K4S64163LH is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,

K4S511632

Abstract: K4S511632M
Contextual Info: K4S511632M CMOS SDRAM 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.3 May. 2002 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.3 May. 2002 K4S511632M CMOS SDRAM Revision History Revision 0.0 Mar. 2001

K4S56163LC

Contextual Info: K4S56163LC-R B F/R CMOS SDRAM 16Mx16 Mobile SDRAM 54CSP (VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR) Revision 1.4 December 2002 Rev. 1.4 Dec. 2002 K4S56163LC-R(B)F/R CMOS SDRAM 4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 2.5V power supply.

Contextual Info: ESMT M52D16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z z z GENERAL DESCRIPTION The M52D16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology.

Contextual Info: H D 6 8 0 1 S0 , H D 6 8 0 1 S 5 MCU M icrocom puter Unit The HD6801S MCU is an 8-bit microcomputer unit which is compatible with the HMCS6800 family of parts. The HD6801S M CU is object code compatible with the HD6800 with im­ proved execution times of key instructions plus several new 16bit and 8-bit instructions including an 8x8 unsigned multiply

TC578200

Abstract: TC538200 TC578200D TC578200D-150
Contextual Info: SILICON STACKED GATE MOS INTEGRATED CIRCUIT TC578200D-150,-200 8 M E G A BIT 524,288 W O R D x 16BIT / 1,048,576 W O R D x 8BIT C M O S U.V, ERA SA B LE A N D ELECTRICALLY P R O G R A M M A B L E REA D O N LY M E M O R Y D ESCRIPTIO N The TC 578200D is a

Contextual Info: Datasheet Serial EEPROM series Standard EEPROM MicroWire BUS EEPROM 3-Wire BR93G76-3A ●General Description BR93G76-3A is serial EEPROM of serial 3-line Interface method. They are 16bit organization and CS PIN is the first PIN in their PIN configuration.

Contextual Info: Datasheet Serial EEPROM series Standard EEPROM MicroWire BUS EEPROM 3-Wire BR93G56-3B General Description BR93G56-3B is serial EEPROM of Serial 3-Line Interface Method. They are 16bit organization and CS PIN is the third PIN in their PIN configuration. Features

TMPZ84

Abstract: TMPZ84C40
Contextual Info: TO SH IBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 /41AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

Contextual Info: TOSHIBA UTOPIA Multiplexer/ De-Multiplexer 1 9 9 T C 3 5 8 8 5 T B R e v i s i o n DAT A TOSHIBA AMERICA ELECTRONIC COMPONENTS, I NC 1. 1 BOOK 9 TO SH IB A Preliminary TC35885TB The contents of this technical data are su bject to change w itho ut advance notice due to

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

1d4 cb

Contextual Info: SN54ABT16373A, SN74ABT16373A 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS S CB S160 - DE CE M B E R 1992 Members of the Texas Instruments Widebus Family SN54ABT16373A . . . WD PACKAGE SN74ABT16373A . . . DGG OR DL PACKAGE TOP VIEW State-of-the-Art EPIC-llB™ BiCMOS Design

Toshiba TB 1230 N

Abstract: TMPZ84C011 TMPZ84C011A TMP284C011 FO34
Contextual Info: TOSHIBA TMPZ84C011A 3. OPERATIONAL DESCRIPTIONS 3.1 ENTIRE BLOCK DIAGRAM AND OPERATION OF EACH BLOCK 3.1.1 Entire Block Diagram 110489 Figure 3.1.1 Entire Block Diagram MPUZ80-302 TOSHIBA TMPZ84C011A 3.1.2 Operation of Each Block The TMPZ84C011A largely consists of a processor MPU , a counter/timer circuit