35RMB Search Results

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

84-PIN

Abstract: CY7C341B
Contextual Info: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

K12J

Abstract: 100-PIN CY7C346 CY7C346B f 7400
Contextual Info: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

C3402

Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Contextual Info: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

74151 PIN DIAGRAM

Abstract: 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C340 CY7C341B CY7C342B
Contextual Info: 40 EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

Contextual Info: '0 CYPRESS Features • 192 m acrocells in 12 L A B s • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

Contextual Info: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

CY7C342

Contextual Info: CY7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the

84-PIN

Abstract: CY7C341 CY7C341B
Contextual Info: CY7C341B ir CYPRESS . Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

Contextual Info: fax id: 6104 CY7C346 CY7C346B W CYPRESS 128-Macrocell MAX EPLDs ture is 100% user configurable, allowing the devices to accom­ modate a variety of independent logic functions. Features • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins

Contextual Info: K? PRELIMINARY ? Js CYPRESS SEMICONDUCTOR = 192-Macrocell MAX EPLD software or by the model shown in Features Logic Array Blocks • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 384 expander product terms

Contextual Info: CYPRESS SEMICONDUCTOR b5E D • SSa^bbS QOlDMbM 27S ■ CYP CY7C341 CY7C341B =- '* ^ 5 = = SEMCONDUCTOR 192-Macrocell MAX EPLD Features Logic Array Blocks • 192 m acrocells in 12 LAlis • 8 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array

c3466

Abstract: C3461 C3467 b4 c346 diode c346 diode IC 7400 SERIES ALL DATA C346 CY7C346 CY7C346B c3468
Contextual Info: fax id: 6104 1CY 7C34 6B CY7C346 CY7C346B 128-Macrocell MAX EPLDs Features ture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins

CY7C342B

Abstract: 7C342B-35 68-PIN CY7C342B15HMB CY7C342B-35RMB CY7C342B-35HC
Contextual Info: 1CY 7C34 2B CY7C342B 128-Macrocell MAX EPLDs Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.

Contextual Info: CY7C346 CY7C346B CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs T h e CY7C346/CY7C346B is an E rasable Program m able Logic Device E P L D in which C M O S E P R O M cells are used to configure logic functions w ithin the device.

tsl-3

Abstract: gear 49t 7C341-40 CY7C341 CY7C341B 38-00137-F 7C341 dd1307h
Contextual Info: CY7C341 CY7C341B if CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array

G013G

Abstract: 05V3 7C342-30 7C342-35 CY7C342 CY7C342B CY7C342-30RMB K941 12J8 CY7C342-35JC
Contextual Info: CY7C342 CY7C342B ^ CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

Contextual Info: CY7C346 CY7C346B STCYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346

CY7C342B-25HMB

Abstract: CY7C342B-35HMB 68-PIN CY7C342B 415l
Contextual Info: # CYPRESS Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Advanced 0.65-micron CMOS technology to increase performance • Available in 68-pin HLCC, PLCC, and PGA Functional Description

LE C346

Abstract: 5067B
Contextual Info: fax id: 6104 CY7C346 CY7C346B 128-Macrocell MAX EPLDs ture is 100% user configurable, allowing the devices to accom ­ modate a variety of independent logic functions. Featu res • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirectional I/O pins

Contextual Info: CYPRESS SEMICONDUCTOR 4bE D B 2 5 0 ^ 2 'T 't- l l y - I V 0007103 T I ICYP 0*7 CY7C342 CYPRESS ß r SEMICONDUCTOR • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC,

Contextual Info: CY7C341 CY7C341B ^CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array