TAC02 Search Results

31-oq

Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
Contextual Info: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

Contextual Info: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools

cy7C344

Abstract: C3M11
Contextual Info: / 9 / I J/ 3 1 Revision: Friday, Apni IS, 1934 CY7C344 f ß CYPRESS i 32-Macrocell MAX FPT P Features Functional Description • High-performance, higfa-deiislty re­ placement for TTL, 74HC, and cus­ tom logic Available in a 28-pin 300-mil DIP or •win­

c3415

Abstract: cy7c341-30jc CY7C341
Contextual Info: CY7C341 y CYPRESS Features • • • • • • 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

CY7C344-25HC

Abstract: 74HC 7C344 C344 CY7C344 000713t Signal path designer IND20 MU2030 AC02X
Contextual Info: 4bE D SEMI CONDUCTOR D 2Sö^bb2 DD07132 ? Q C Y P ‘T ' & ' M - O l W s CYPRESS SEMICONDUCTOR CY7C344 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and custom logic • 32 macroceils, 64 expander product

wl1251

Abstract: 464X1
Contextual Info: CY7C341 PRELIMINARY r CYPRESS SEMICONDUCTOR 192-Macrocell MAX EPLD Features Logic A rray Blocks • 192 macrocells in 12 LABa T h e re are 12 logic array blocks in the CY7C341. Each LAB consists o f a m acro ­ cell array containing 16 m acrocells, an ex­

C3424

Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
Contextual Info: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342

D85C060-25

Abstract: PLD610 85C060 P85C060-25 PLD610-25 P85C060-15 D85C060-10 intel 85C060 n85c060 pld610-15
Contextual Info: intel ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610, 85C060 and 5C060 PLDs • tpD 10 ns, 100 M H z C o u n te r F req u en cy w /ln te rn a l F e e d b a c k ■ E xte n s ive S o ftw a re an d P ro g ram m in g

Cypress cy7c344

Abstract: 74HC 7C344 C344 CY7C344 CY7C344B TW417
Contextual Info: CY7C344 CY7C344B CYPRESS 32-Macrocell MAX EPLD Features Functional Description • A v ailab le in a 2 8 -p in 300-m il DTP o r w in ­ d o w e d J -le a d e d c e ra m ic c h ip c a rrie r H L C C , th e C Y 7 C 3 4 4 /C Y 7 C 3 4 4 B r e p r e ­ s e n ts th e d e n s e s t E P L D o f th is size. E ig h t

pin configuration IC 74151

Abstract: IC 74151 diagram and truth table IC TTL 7400 diagram and truth table ic 74151 full adder using Multiplexer IC 74151 Multiplexer IC 74151 programmer manual EPLD cypress IC 7400 SERIES ALL DATA programming manual EPLD cy7c342
Contextual Info: CYPRESS SEMICONDUCTOR HOE D 256*^2 DD05427 5 ICYP 7 T V d -/3 -4 7 CY7C340 EPLD Family « 1 ^ CYPRESS SEMICONDUCTOR Multiple Array Matrix High-Density EPLDs Features General Description • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions

Contextual Info: CY7C342 CY7C342B CYPRESS SEMICONDUCTOR & 128-Macrocell M A X EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • Available in 68-pin HLCC, PLCC, PGA, and Flatpack

Contextual Info: fax id: 6102 CY7C343 CY7C343B W CYPRESS 64-Macrocell MAX EPLD Features Functional Description • • • • 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology

Contextual Info: CY7C343 CY7C343B CYPRESS 64-Macrocell MAX EPLD Features Functional Description • • • • 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology CY7C343

100-PIN

Abstract: CY7C346 CY7C346B gogo board K1268
Contextual Info: fax id: 6104 CY7C346 CY7C346B 128-Macrocell MAX EPLDs Features ture is 100% user configurable, allowing the devices to accom­ modate a variety of independent logic functions. • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins

CY7C343

Abstract: CY7C343B
Contextual Info: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Features • • • • 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology CY7C343

84-PIN

Abstract: CY7C341 CY7C341B
Contextual Info: CY7C341B ir CYPRESS . Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and

74HC

Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131
Contextual Info: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

DD131

Contextual Info: CY7C343 CY7C343B CYPRESS 64-Macrocell MAX EPLD Functional Description Features • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS E P R O M technology CY7C343

Contextual Info: CY7C344 CY7C344B m w CYPRESS 32-Macrocell MAX EPLD F eatures F unctional D escription • High-performance, high-denslty re­ placement for TTL, 74HC. and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: CY7C342B S / CYPRESS Features • 128-Macrocell MAX EPLDs m a b lc L ogic D evice E P L D in w h ich C M O S E P R O M c e lls a re u se d to c o n fig u re logic fu n c tio n s w ith in th e d ev ice. T h e M A X a rc h ite c tu re is 100% u s e r c o n fig u r­

Contextual Info: K? PRELIMINARY ? Js CYPRESS SEMICONDUCTOR = 192-Macrocell MAX EPLD software or by the model shown in Features Logic Array Blocks • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 384 expander product terms

dpld910

Abstract: pld910 IPLD910-25 DPLD910-15 adf simu 5C090 tcl eprom intel PLD INTEL PLD910 adf compiler
Contextual Info: i n t j . ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP91QA, 85C090 and 5C090 m tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns • Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 ju.A Typ. in

CY7C343

Abstract: CY7C343B
Contextual Info: CY7C343 » T C Y PR ESS Features CY7C343B 64-Macrocell MAX EPLD Functional Description • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C343