32DIP Search Results

lh537

Abstract: 42DIP lh533200 LH535g
Contextual Info: MEMORIES • Mask ROMs Process CMOS ★ U n d e r development MEMORIES ★ Under developm ent Configuration Process Capacity (wortsxbits Access time (ns) MAX. Model No. Pinout LH-538VXX 100 100 5 ± 10% 32DIP/32SOP/32TSOPÎII) Normal 120 60 5 ± 10% L H 5 3 8 3 0 0 C D /C W C S Æ S H

32DIP

Abstract: IC128 27nC
Contextual Info: App87Lx-3.2 June 6, 1996 MICROCONTROLLER TECHNOLOGY PROGRAMMER SUPPORT APPLICATION NOTE SCOPE: COP87Lxx Family Third-party Programming Adapters. Adapters are available which allow programming all family devices from a single 32 pin DIP pinout Select COP87Lxx-32 Adapter from the programmer menu . The 32DIP pinout mapping

WSP-401M

Abstract: BD103 dms-200d bd102 transisTOR C123 2N5401C-Y DG04 rsb7 sk101 S1D2514X01
Contextual Info: S1D2514X01 Preliminary VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS VIDEO AMP MERGED OSD PROCESSOR 32-DIP-600A The S1D2514X01 is a very high frequency video amplifier & wide range OSD processor 1 chip system with I2C Bus control used in monitors. It contains 3 matched R/G/B video

K8D3216UBC-pi07

Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
Contextual Info: Product Selection Guide Memory and Storage April 2005 MEMORY AND STORAGE SECTION A DRAM DDR2 SDRAM DDR SDRAM SDRAM RDRAM NETWORK DRAM MOBILE SDRAM GRAPHICS DDR SDRAM DRAM ORDERING INFORMATION FLASH NAND, OneNAND, NOR FLASH NAND FLASH ORDERING INFORMATION SRAM

KM681001-25

Abstract: KM681001-20 KM681001-35 tl2245 KM681001
Contextual Info: KM681001 CMOS SRAM 128K x 8 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 20,25,35 ns Max. • Low Power Dissipation Standby (TTL) : 40 mA(Max.) (CMOS): 2 mA(Max.) Operating KM681001-20 : 170 mA(Max.) KM681001-25:150 mA(Max.)

TAA 310A

Abstract: KM681000BLP-7L 128k x8 SRAM TSOP km681000blp-7 KM681000B KM681000BL KM681000BLE KM681000BL-L
Contextual Info: KM681000B Family CMOS SRAM 128Kx8 bit High Speed CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology: 0.6 um CMOS • Organization : 128K x 8 • Power Supply Voltage : Single 5V +/-10% • Low Data Retention Voltage : 2V Min • Three state output and TTL Compatible

TSOP 173 g

Abstract: KM684000ALG-7 4000 CMOS KM684000ALGI-7L KM684000ALP-7L KM684000ALP-5L KM684000A KM684000AL KM684000ALI KM684000ALI-L
Contextual Info: i, CMOS SRAM KM684000A Family 512Kx8 bit High Speed CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology: 0.4 um CMOS The KM684000A family is fabricated by SAMSUNG'S advanced CMOS process technology. The family • Organization : 512K x8

A1SH

Abstract: 32DIP 32-PIN LH532100B-1 A14C
Contextual Info: LH532100B-1 FEATURES CMOS 2M 256K x 8 Mask-Programmable ROM PIN CONNECTIONS • 262,144 words x 8 bit organization • Access time: 120 ns (MAX.) 32-PIN DIP 32-PIN SOP TOP VIEW f \ O E ^ O E i/D C C • Static operation • TTL compatible I/O • Three-state outputs

KM684000BLP-7

Abstract: KM684000B KM684000BL KM684000BLI KM684000BLI-L KM684000BL-L KM684000BLP-5 KM684000BLP-5L KM684000BLP-7L KM684000BLG-7L
Contextual Info: Prem iìinary CMOS SRAM KM684000B Family 512Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION ~ - The KM684000B family is fabricated by SAMSUNG'S advanced CMOS process technology. The family can support various operating temperature ranges and has various package types

16MB SRAM

Abstract: 1024k DS1270W DS1249W DS1265W 36-DIP
Contextual Info: INDUSTRY’S HIGHEST DENSITY 3.3V NONVOLATILE SRAMs Densities up to 16Mb Protect Data for 3.3V Systems The DS1249W, DS1265W, and DS1270W are low-voltage, high-density NV SRAMs designed to preserve critical system data during power loss. Each of these dual in-line encapsulated modules operates on a single 3.3V power supply and employs

s134 p-mosfet

Abstract: 74hc260 Mitsumi D359T3 D359T3 schematic diagram inverter lcd monitor fujitsu 62256-10 BERG STRIP teac fd 235hf stepping motor mitsumi mitsumi floppy
Contextual Info: frt Page 1 Thursday, August 8, 1996 12:36 PM ÉlanSC300 Microcontroller Evaluation Board User’s Manual evalbd.book : frt Page 2 Thursday, August 8, 1996 12:14 PM ÉlanSC300 Microcontroller Evaluation Board, Revision 1.1 1996 by Advanced Micro Devices, Inc.

Mitsumi D359T3

Abstract: D359T3 Video Card AVED AV540 mitsumi floppy d359* mitsumi SCHEMATIC TRIDENT VGA board EPROM AMD s134 p-mosfet stepping motor mitsumi 62256-10
Contextual Info: evalbd.book : frt Page 1 Thursday, August 8, 1996 2:34 PM ÉlanSC310 Microcontroller Evaluation Board User’s Manual evalbd.book : frt Page 2 Thursday, August 8, 1996 2:34 PM ÉlanSC310 Microcontroller Evaluation Board, Revision 1.0 1996 by Advanced Micro Devices, Inc.

MR27V401E

Abstract: MR27V401EMA MR27V401ERA MR27V401ETA
Contextual Info: Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008.

23C4000

Contextual Info: GM23C4000 GoldStar 524,288 WORDS x 8 BIT CMOS MASK ROM GOLDSTAR ELECTRON CO., LTD. Pin Configuration 32 DIP Top View D escription The G M 23C 4000 high-perform ance Read Only M em ory is organized as 524,288 w ords by eight bits and has an access tim e o f 150/200ns. It is

pal 007c

Abstract: b1100 nec LDP16 sulzer s7 7-segment countdown timer MDP36 100LQ128 3pin round shell connector DP83932B LT1084CT-3.3
Contextual Info: MiniRISC BDMR4011 Evaluation Board User’s Guide A CoreWare® Product March 1998 ® Order Number XXXXX Document DB15-000055-00, First Edition March 1998 This document describes revision A of LSI Logic Corporation’s BDMR4011 Evaluation Board and will remain the official reference source for all revisions/releases of this product until rescinded by an update.

MAX147

Contextual Info: 19-0465; Rev 2; 10/01 KIT ATION EVALU E L B A AVAIL +2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically

K6X1008C2D-GF55

Abstract: K6X1008C2D-TF55 K6X1008C2D-TB55 K6X1008C2D-F samsung k6x1008c2d K6X1008C2D-TF70
Contextual Info: Preliminary CMOS SRAM K6X1008C2D Family Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft July 15, 2002 Preliminary 0.1 Revised - Deleted 32-TSOP1-0820R Package Type. - Added Commercial product.

K6T1008C2E-GB70

Abstract: K6T1008C2E-TB55
Contextual Info: K6T1008C2E Family CMOS SRAM Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Design target October 12, 1998 Preliminary 1.0 Finalize - Improve tWP form 55ns to 50ns for 70ns product. - Remove 55ns speed bin for industrial product.

lh5s4

Abstract: lh5348 LH5s lh5s47xx 48-TSOP LH53H4100D LH53H4100N lh534y00d 48TSOP sharp mask rom
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53 H4100 • Description High-speed 4M-bit Mask-Programmable ROM ■ Pin Connections The LH53H4100D/N User's No. ! LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

Contextual Info: KM23C8000B G ELECTRONICS CMOS Mask ROM 8M-Bit (1M X8) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • 1,048,576x 8 bit organization • Fast access time :100ns(max.) • Supply voltage : single +5V • Current consumption Operating : 60 mA(max.) Standby : 50 fiA (max.)

Contextual Info: KM684000A Family_ CMOS SRAM 512Kx8 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION •• Process Technology : 0.4 * CMOS •• Organization : 512Kx8 •■ Power Supply Voltage : Single 5V •• 10% ■ Low Data Retention Voltage : 2V Min

Contextual Info: PRELIMINARY KM23C8001H CMOS MASK ROM 8M-Bit 1M X 8 CMOS MASK ROM FEATURES GENERAL DESCRIPTION • • • • The KM23C8001H is a fully static mask programmable ROM organized 1 ,0 4 8 ,5 7 6 X 8 bit. It is fabricated using silicon-gate CMOS process technology.

Contextual Info: KM681000B Family CMOS SRAM Document Title 128K x8 bit Low Power CMOS Static RAM Revision History History Draft Data Remark 0.0 Initial draft for com m ercial product - Com mercial Product only O ctober 28th, 1992 Prelim inary 0.1 - Initial draft for Extended/Industrial Product

Contextual Info: KM23C4000D G CMOS MASK ROM 4M-Bit (512Kx8) CMOS MASK ROM GENERAL DESCRIPTION FEATURES • • • • • • • • 524,288x8 bit organization Access tim e : 80ns(M ax.) Supply voltage : single +5V Current consumption Operating : 50m A(M ax.) Standby : 50|iA(M ax.)