2MX8 Search Results
2MX8 Result Highlights (1)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| DS90CP22MX-8/NOPB | Texas Instruments | 800 Mbps 2x2 LVDS Crosspoint Switch 16-SOIC -40 to 85 |
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2MX8 Price and Stock
LEDIL CS15765_HB-2X2MX-8-WWW- Trays (Alt: CS15765_HB-2X2MX-8-WWW) |
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CS15765_HB-2X2MX-8-WWW | Tray | 10 Weeks | 52 |
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CS15765_HB-2X2MX-8-WWW | 7 Weeks | 52 |
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CS15765_HB-2X2MX-8-WWW | 7 Weeks | 52 |
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LEDIL CS15751_STRADA-2X2MX-8-DWC- Trays (Alt: CS15751_STRADA-2X2MX-8-DWC) |
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CS15751_STRADA-2X2MX-8-DWC | Tray | 10 Weeks | 52 |
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CS15751_STRADA-2X2MX-8-DWC | 7 Weeks | 52 |
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CS15751_STRADA-2X2MX-8-DWC | 7 Weeks | 52 |
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LEDIL CS15767_HB-2X2MX-8-M- Trays (Alt: CS15767_HB-2X2MX-8-M) |
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CS15767_HB-2X2MX-8-M | Tray | 10 Weeks | 52 |
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CS15767_HB-2X2MX-8-M | 7 Weeks | 52 |
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CS15767_HB-2X2MX-8-M | 7 Weeks | 52 |
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LEDIL CS15759_HB-2X2MX-8-W- Trays (Alt: CS15759_HB-2X2MX-8-W) |
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CS15759_HB-2X2MX-8-W | Tray | 10 Weeks | 52 |
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CS15759_HB-2X2MX-8-W | 7 Weeks | 52 |
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LEDIL CS15750_STRADA-2X2MX-8-T4-B- Trays (Alt: CS15750_STRADA-2X2MX-8-T4-B) |
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CS15750_STRADA-2X2MX-8-T4-B | Tray | 10 Weeks | 52 |
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CS15750_STRADA-2X2MX-8-T4-B | 7 Weeks | 52 |
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CS15750_STRADA-2X2MX-8-T4-B | 7 Weeks | 52 |
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2MX8 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: 32MB 168PIN PC66 SDRAM DIMM With 2M X 8 3.3VOLT TS4MLS64V1P2N Description Placement The TS4MLS64V1P2N is a 4M bit x 64 Synchronous Dynamic RAM, high density for PC-66. The TS4MLS64V1P2N consists of 16pcs CMOS 2Mx8 bits Synchronous DRAMs in TSOP-II 400mil packages and a |
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168pints4mls64v1p2npc-6616pcs+2 | |
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Contextual Info: •HYUNDAI H Y 5 1 17 8 0 4 B ,H Y 5 1 16 8 0 4 B 2Mx8, Extended Data Out mode DESCRIPTION This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process |
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Contextual Info: • HY UNDAI HYCFLF16008 Series _8MB x8/x16 Configurable FLASH Memory CARD DESCRIPTION The HYCFLF16008 is the Flash memory card consisting of four 5V-only 16Mbit 2Mx8 Flash memory chips in a metal plate housing. The Hyundai Rash memory card is optimized for the application of data and file storage in |
OCR Scan |
hycflf16008x8/x1616mbit00031flfl+2 | |
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Contextual Info: 16Mbit Synchronous DRAM Series ♦HYUNDAI HY57V164010- 4Mx4bit Synchronous DRAM HY57V168010- 2Mx8blt Synchronous DRAM HY57V161610- 1Mx16bit Synchronous DRAM DESCRIPTION The HY57V164010, HY57V168010, HY57V161610 Programmable options include the length of are high speed 3.3 Volt synchronous dynamic RAMs |
OCR Scan |
16mbithy57v164010-hy57v168010-hy57v161610-+6 | |
sm 0038 tsop
Abstract: E-8BS16
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msc23s4641e-8bs1664bit168-pin+2 | |
1MX16
Abstract: CCIR601 CCIR656 PBGA388
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64-bit66mhz16mbit1mx16+4 | |
MSC23S4721E-8BS18Contextual Info: MSC23S4721E-8BS18 98.07.17 Semiconductor MSC23S4721E-8BS18 4,194,304 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK): DESCRIPTION The Oki MSC23S4721E-8BS18 is a fully decoded, 4,194,304 x 72bit synchronous dynamic random access memory composed of eighteen 16Mb DRAMs (2Mx8) in TSOP |
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msc23s4721e-8bs1872bit168-pin72-bit | |
MSC23S2640E-8BS8Contextual Info: MSC23S2640E-8BS8 98.08.19 Semiconductor MSC23S2640E-8BS8 2,097,152 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK): DESCRIPTION The Oki MSC23S2640E-8BS8 is a fully decoded, 2,097,152 x 64bit synchronous dynamic random access memory composed of eight 16Mb DRAMs (2Mx8) in TSOP |
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msc23s2640e-8bs864bit168-pin64-bit | |
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Contextual Info: 0316409C 4M x 412/10, 3.3V, SR. 0316169C 1M x 1612/8, 3.3V, SR. 0316809C 2M x 812/9, 3.3V, SR. 4Mx4, 2Mx8, 1Mx16 16Mbit Enhanced Synchronous DRAM Preliminary Features • High Performance: CAS latency = 2 fCK Clock Frequency tCK2 Clock Cycle tAC2 Clock Access Time |
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0316409c0316169c0316809c1mx16+3 | |
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Contextual Info: 0316409C 4M x 412/10, 3.3V, SR. 0316169C 1M x 1612/8, 3.3V, SR. 0316809C 2M x 812/9, 3.3V, SR. 4Mx4, 2Mx8, 1Mx16 16Mbit Enhanced Synchronous DRAM Preliminary Data Sheet Overview Features • High Performance: CAS latency = 2 • Programmable Burst Length: 1,2,4,8,full-page |
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0316409c0316169c0316809c1mx16+6 | |
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Contextual Info: K3N5V U 1000E-D(G)C CMOS MASK ROM 16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 2,097,152 x 8(byte mode) 1,048,576 x 16(word mode) • Fast access time 3.3V Operation : 100ns(Max.)@CL=50pF, 120ns(Max.)@CL=100pF |
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1000e-d16m-bit/1mx16100ns+4 | |
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Contextual Info: K3P5C1000D-D G C CMOS MASK ROM 16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 2,097,152 x 8(byte mode) 1,048,576 x 16(word mode) • Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) 8 Words / 16 Bytes page access |
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k3p5c1000d-d16m-bit/1mx16100ns+5 | |
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Contextual Info: K3N5V U 1000E-TC CMOS MASK ROM 16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 2,097,152 x 8(byte mode) 1,048,576 x 16(word mode) • Fast access time 3.3V Operation : 100ns(Max.)@CL=50pF, 120ns(Max.)@CL=100pF 3.0V Operation : 120ns(Max.)@CL=100pF |
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1000e-tc16m-bit/1mx16100ns+3 | |
pc133 SDRAM DIMM
Abstract: 64814GSEM4G09T PC133
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pc-13364814gsem4g09t8mx64256x8+2 | |
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F25L016A
Abstract: SOIC 200mil
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f25l016a16mbit33mhz50mhz+3 | |
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Contextual Info: MEMORY 2Mx84BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM M 2SO64CE-100/-84/-67/-100L/-84 L/-67L/-100S/-84S/-67S 144-pin, 2 Clock, 1-bank, based on 2 M x 8 Bit SDRAMs with SPD, Low-power version DESCRIPTION The Fujitsu MB8502S064CE is a fully decoded, CMOS Synchronous Dynamic Random Access Memory |
OCR Scan |
2mx84bit2so64ce-100/-84/-67/-100l/-84l/-67l/-1+4 | |
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Contextual Info: SMART SM5720280UUDUGU Modular Technologies February 18, 1998 16MByte 2M x 72 DRAM Module - 2Mx8 based 168-pin DIMM, Non-buffered, ECC Features Part Numbers • • • • • • • • • • • SM57202800UDUGU SM57202801UDUGU SM57202808UDUGU SM57202809UDUGU |
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sm5720280uudugu16mbyte168-pinsm57202800udugu+6 | |
xxxxxxxxxContextual Info: LY62L102616A Rev. 1.1 16M Bits 2Mx8 / 1Mx16 Switchable LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Correct typo error on the column “UB#”, “LB#” of truth table for row “Byte Read” “Byte Write” and “Output Disable” at |
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ly62l102616a1mx16ly62l102616all-55sltly62l102616all-55sl+2 | |
SIMM 80 jedec
Abstract: 80 pin simm flash Flash SIMM 80 E28F016S5 EDI7F342MC
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edi7f342mc2mx32edi7f2342mce28f016s5+6 | |
16202
Abstract: HY23V16202 HY23V16202D HY23V16202S HY23V16202T 48TSOP
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1mx16/2mx8hy23v1620242pin100/120ns+6 | |
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Contextual Info: KM23C16005D G CMOS MASK ROM 16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 2,097,152 x 8(byte mode) 1,048,576 x 16(word mode) • Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) 8 Words / 16 Bytes page access |
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km23c16005d16m-bit/1mx16100ns+5 | |
IR 10D 8AContextual Info: K7I163684B K7I161884B K7I160884B Advance 512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. 0.0 History 1. Initial document. Draft Date Remark Dec. 16, 2002 Advance The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the |
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k7i163684bk7i161884bk7i160884b512kx36+4 | |
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Contextual Info: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram |
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k7j163682bk7j161882bk7j160882b512kx36+4 | |
28F016S3
Abstract: EDI7F342MV 80pin-SIMM
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edi7f342mv2mx327f2342mv28f016s3+4 | |