2DS1 Search Results

BVA-24BS2.4

Abstract: 12-A-S-1 BVA-2DS12 BVA-5AS3-OVP Fuse 300V 2A BVA-12FS16 BVA-28AS1 BVA-2ES18 2DS12 BVA-15BS3
Contextual Info: Single Ouput, Linear 1950 950 Selection Guide Partial See pages 10 — 11 for dimension drawings Single Output Models Model 2 VOLTS BVA-2AS3 BVA-2BS6 BVA-2DS12 BVA-2ES18 Case 2 VOLTS Output 2 VOLTS AS BS DS ES 2V 2V 2V 2V @ @ @ @ 3A 6A 12A 18A 5 VOLTS BVA-5AS1.5-OVP

MSC5301B-01GS-BK

Abstract: 11 pin 8 segment LcD MSC5301B-01 QFP100-P-1420-BK C14EE
Contextual Info: O K I Semiconductor MSC5301B-01 COMMON/SEGMENT DRIVER WITH RAM GENERAL DESCRIPTION The MSC5301B-01 is an LCD driver LSI w ith a built-in RAM. The device's bit m apping m ethod offers greater flexibility in w hich each bit of the RAM for display controls each section on the LCD

DS 2020

Abstract: CY7B993V CY7B994V JESD22-A114 LCK4993 LCK4993YH-DB LCK4993YH-DT LCK4994 chilled water system
Contextual Info: Data Sheet, Revision 1 May 5, 2004 LCK4993/LCK4994 Low-Voltage PLL Clock Drivers 1 Features • 12 MHz—100 MHz LCK4993 , or 24 MHz—200 MHz (LCK4994) output operation ■ Matched pair output skew <200 ps ■ Zero input-to-output delay ■ 18 LVTTL 50% duty-cycle outputs capable of driving

CY7B9945V

Abstract: CY7B9945V-2AC CY7B9945V-2AI CY7B9945V-5AC CY7B9945V-5AI
Contextual Info: 945V RoboClock II CY7B9945V High-Speed Multi-Phase PLL Clock Buffer Features Functional Description • 24–200 MHz output operation • Low output-output skew < 200 ps • 10 + 1 LVTTL 50% duty cycle outputs capable of driving 50Ω terminated lines • Dedicated feedback output

Contextual Info: Wire Guard | Spacing 10.0 mm AK500/.DS-10.0-V-GREY -BL Order Data Spacing 10.0 mm Technical Data Article Designation Article Number Solid min 0.2 mm² Material PA 6.6 2 15.00 AK500/2DS-10.0-V-GREY -BL 50500023211G 250 solid max 1.5 mm² Flammability Class

Contextual Info: Wire Guard | Spacing 10.0 mm AK500/.DS-10.0-V-GREY Order Data Spacing 10.0 mm Technical Data Article Designation Article Number Solid min 0.2 mm² Material PA 6.6 2 15.60 AK500/2DS-10.0-V-GREY 50500020211G 250 solid max 1.5 mm² Flammability Class UL 94 V-0

Contextual Info: Wire Guard | Spacing 10.0 mm AK100/.DS-10.0-H-GREY Order Data Spacing 10.0 mm Technical Data Article Designation Article Number Solid min 0.2 mm² Material PA 6.6 2 15.70 AK100/2DS-10.0-H-GREY 50100020240G 250 solid max 4.0 mm² Flammability Class UL 94 V-0

52-PIN hm 2007

Abstract: CY7B9945V CY7B9945V-2AXC CY7B9945V-2AXCT CY7B9945V-2AXIT CY7B9945V-5AXC CY7B9945V-5AXCT
Contextual Info: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB™ window ■ 24–200 MHz input and output operation ■ Low output-output skew < 200 ps ■ 10 + 1 LVTTL outputs driving 50W terminated lines

CY7B9945V

Abstract: CY7B9945V-2AXC CY7B9945V-2AXCT CY7B9945V-2AXIT CY7B9945V-5AXC CY7B9945V-5AXCT HWT 09 322f
Contextual Info: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB window ■ 24 MHz –200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL Outputs driving 50Ω terminated lines

U4B R950

Abstract: PC MOTHERBOARD GIGABYTE CIRCUIT diagram SCHEMATIC gigabyte MOTHERBOARD CIRCUIT diagram C828 3-pin transistor C1162 transistor C1162 gigabyte g31 MOTHERBOARD SERVICE MANUAL emp3128 transistor C1162 Scheme motorola r1009
Contextual Info: MPC8560 PowerQUICC III Torridon User’s Guide MPC8560UG Rev. 0.1 12/2004 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370

Contextual Info: RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation ■ Matched Pair Output Skew < 200 ps

LCK4993V

Abstract: CY7B993V CY7B994V JESD22-A114 LCK4994 LCK4994V
Contextual Info: Advance Data Sheet November 2002 LCK4993V/LCK4994V Low-Voltage PLL Clock Drivers Features • 12/100 MHz LCK4993V , or 24/200 MHz (LCK4994V) output operation ■ Matched pair output skew <200 ps ■ Zero input-to-output delay ■ ■ ■ ■ ■ ■ ■ 18 LVTTL 50% duty-cycle outputs capable of

CY7B993V

Abstract: CY7B993V-2AC CY7B993V-2AI CY7B994V CY7B994V-2AC
Contextual Info: RoboClock CY7B994V CY7B993V High-speed Multi-phase PLL Clock Buffer Features • 500-ps max. Total Timing Budget TTB™ window • 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V) output operation • Matched pair output skew < 200 ps • Zero input-to-output delay

CY7B993V

Abstract: CY7B994V LCK4993 LCK4994
Contextual Info: Advance Data Sheet December 4, 2003 LCK4993/LCK4994 Low-Voltage PLL Clock Drivers 1 Features • 12 MHz—100 MHz LCK4993 , or 24 MHz—200 MHz (LCK4994) output operation ■ Matched pair output skew <200 ps ■ Zero input-to-output delay ■ ■ ■ 18 LVTTL 50% duty-cycle outputs capable of driving

Contextual Info: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB window ■ 24 MHz –200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL outputs driving 50Ω terminated lines

CY7B993V

Abstract: CY7B994V
Contextual Info: RoboClock, CY7B994V CY7B993V PRELIMINARY High-Speed Multi-Phase PLL Clock Buffer Features Functional Description • 12/100-MHz CY7B993V , or 24/185-MHz (CY7B994V) output operation • Matched pair outputs skew <200 ps • Zero input-to-output delay • 18 LVTTL 50% duty-cycle outputs capable of driving

2DS1

Abstract: CY7B993V CY7B994V 24185
Contextual Info: RoboClockII CY7B994V ADVANCED INFORMATION CY7B993V High-Speed Multi-Phase PLL Clock Buffer Features • Matched pair outputs skew <200 ps 200 ps MAX • 3.3V BiCMOS Technology • 12−100 MHz (CY7B993V), or 24−185 MHz (CY7B994V) output operation • 18 3.3V LVTTL outputs

Contextual Info: 94V RoboClockII CY7B994V CY7B993V High-Speed Multi-Phase PLL Clock Buffer Features Functional Description • 12/100-MHz CY7B993V , or 24/200-MHz (CY7B994V) output operation • Matched pair output skew <200 ps • Zero input-to-output delay • 18 LVTTL 50% duty-cycle outputs capable of driving

Contextual Info: RoboClock CY7B993V, CY7B994V High Speed Multi Phase PLL Clock Buffer Features Functional Description • 500 ps Max Total Timing Budget TTB window ■ 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation ■ Matched Pair Output Skew < 200 ps

Contextual Info: RoboClock CY7B9945V PRELIMINARY High Speed Multi-phase PLL Clock Buffer Features Functional Description • 500 ps max Total Timing Budget TTB window The CY7B9945V high speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple

Contextual Info: Wire Guard | Spacing 10.0 mm AK500/.DS-10.0-H-GREY -BL Order Data Spacing 10.0 mm Technical Data Article Designation Article Number Solid min 0.2 mm² Material PA 6.6 2 15.00 AK500/2DS-10.0-H-GREY -BL 50500023241G 250 solid max 1.5 mm² Flammability Class

Contextual Info: Wire Guard | Spacing 10.16 mm AKZ500/.DS-10.16-V-GREY Order Data Spacing mm Technical Data Article Designation Article Number Solid min 0.2 mm² Material PA 6.6 2 15.84 AKZ500/2DS-10.16-V-GREY 50500020224G 250 solid max 1.5 mm² Flammability Class UL 94 V-0

CY7B993V

Abstract: CY7B993V-5AC CY7B993V-5AI CY7B994V CY7B994V-5AC CY7B994V-5AI
Contextual Info: RoboClockII CY7B994V CY7B993V PRELIMINARY High-Speed Multi-Phase PLL Clock Buffer Features Functional Description • 12/100-MHz CY7B993V , or 24/185-MHz (CY7B994V) output operation • Matched pair outputs skew <200 ps • Zero input-to-output delay • 18 LVTTL 50% duty-cycle outputs capable of driving

Contextual Info: Replace MPC973 with RoboClock II Introduction Cypress CY7B993 and CY7B994 RoboClock II contain a comprehensive feature set that performs a superset of those contained in the Motorola MPC973 and MPC972. Systems that were originally designed around the Motorola part can be