2DP1 Search Results

Contextual Info: 2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to 10 LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL

Input voltage 40V Output voltage 13.8V

Abstract: JEDEC SPEC MS - 034 JESD78B
Contextual Info: 2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage positive emitter-coupled logic LVPECL input pairs to distribute to 10 LVPECL output pairs ■ 40-ps maximum output-to-output skew

CBTV4010

Abstract: ICS83840B ICS83840BH ICS83840BHT 2dp3 marking NS1 1DP6
Contextual Info: PRELIMINARY ICS83840B Integrated Circuit Systems, Inc. DDR SDRAM MUX GENERAL DESCRIPTION FEATURES The ICS83840B is a DDR SDRAM MUX and is a ICS member of the HiPerClockS family of High PerforHiPerClockS mance Clock Solutions from ICS. The device has 10

P332D

Abstract: P103E P822D P822E
Contextual Info: Aluminum Electrolytic Capacitors Large Can Type Series GUP Series GUP Features • High C V value with expanded case size «>0.4 x 108 - tj>90 x 222 ■ High ripple current approx. 1 . 5 - 2 times of GYU-series) Specifications Item Perform ance Characteristics

sharp mask rom 44-pin

Abstract: PIP02 register file LH080 LH0881 LH0811 LH081 R255
Contextual Info: Z8 Microcomputer Unit ROMIess LH0881 /LH0881A Microcomputer Unit LH0881/LH0881A Z8(ROMIess) • Description Pin Connections T h e L H 0 8 8 1 / A is a ROMIess v ersio n of the L H 0 8 0 1 /A and L H 0 8 1 1 / A Z8 single-chip micro­ computers and offers the outstanding feature of the

Contextual Info: CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 4 — 18 June 2012 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin HPn is multiplexed to one of four DIMM port pins (xDPn). The

4B 22 25V

Abstract: CBTV4010 ICS3840ALF ICS83840 ICS83840AH ICS83840AHLF ICS83840AHLFT ICS83840AHT hp8k tfBGA 8 x 8 tray
Contextual Info: ICS83840 Integrated Circuit Systems, Inc. DDR SDRAM MUX GENERAL DESCRIPTION FEATURES The ICS83840 is a DDR SDRAM MUX and is a member of the HiPerClock S family of High HiPerClockS™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can

Contextual Info: 2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz

CBTU4411EE

Abstract: JESD22-A114 JESD22-A115 JESD78 2dp1
Contextual Info: INTEGRATED CIRCUITS CBTU4411 11-bit DDR2 SDRAM mux/bus switch with 12 Ω on-resistance Product data sheet Supersedes data of 2005 Jan 07 Philips Semiconductors 2006 Sep 22 Philips Semiconductors Product data sheet 11-bit DDR2 SDRAM mux/bus switch with 12 Ω on-resistance

JESD78

Abstract: TFBGA64 CBTV4010 CBTV4010EE JESD22-A114 JESD22-A115 SA00589
Contextual Info: INTEGRATED CIRCUITS CBTV4010 10-bit DDR SDRAM mux/bus switch Product data File under Integrated Circuits — ICL03 Philips Semiconductors 2002 Feb 19 Philips Semiconductors Product data 10-bit DDR SDRAM mux/bus switch CBTV4010 FEATURES DESCRIPTION • Enable signal is SSTL_2 compatible

Contextual Info: 2DP1502 1:2 LVPECL Fanout Buffer Functional Description Features • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz

JESD78B

Abstract: cy2d
Contextual Info: 2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One low-voltage positive emitter-coupled logic LVPECL input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■

sdram schematic diagram

Abstract: ICS384 CBTV4010 ICS252 ICS3840BLF ICS650-40A ICS83840B ICS83840BH ICS83840BHLF ICS83840BHLFT
Contextual Info: DATA SHEET ICS83840B ICS83840B Integrated DDR SDRAM MUX Circuit DDR SDRAM MUX Systems, Inc. GENERAL DESCRIPTION FEATURES The ICS83840B is a DDR SDRAM MUX and is ICS a member of the HiPerClockS family of High HiPerClockS™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can

p181s

Abstract: 30pos 1F21030
Contextual Info: FUTURE BUS CONNECTOR SPECIFICATIONS 1F Series Header. Press Fit Type 2.0mm Pitch 5 Row s Mechanical Contact Retention Force: 1.0Kg min. Electrical Voltage Rating: 750V Current Rating: 1A Contact Resistance: 55mΩ max. Dielectrical Withstanding Voltage: 1000V

Contextual Info: 2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage positive emitter-coupled logic LVPECL input pairs to distribute to four LVPECL output pairs ■ 30 ps maximum output-to-output skew

Contextual Info: HARRIS SENICOND SECTOR 4302271 0D3fi5SS 3 4bE D IHAS CDP1877 CDP1877C HARRIS SEMICONDUCTOR Programmable Interrupt Controller PIC February 1992 Features Description • Compatible with CDP1800 Series The CDP1877 and CDP1B77C are programmable 8-level interrupt control­

sdram schematic diagram

Abstract: CBTV4010 ICS252 ICS3840ALF ICS650-40A ICS83840 ICS83840AH ICS83840AHLF ICS83840AHLFT ICS83840AHT
Contextual Info: DATA SHEET ICS83840 ICS83840 Integrated DDR SDRAM MUX Circuit DDR SDRAM MUX Systems, Inc. GENERAL DESCRIPTION FEATURES The ICS83840 is a DDR SDRAM MUX and is a member of the HiPerClock S family of High HiPerClockS™ Performance Clock Solutions from ICS. The

Contextual Info: 2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input 1:4 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVPECL output pairs

2dp3

Abstract: CBTV4010 ICS3840BLF ICS83840B ICS83840BH ICS83840BHLF ICS83840BHLFT ICS83840BHT 4318C tsa11
Contextual Info: ICS83840B Integrated Circuit Systems, Inc. DDR SDRAM MUX GENERAL DESCRIPTION FEATURES The ICS83840B is a DDR SDRAM MUX and is ICS a member of the HiPerClockS family of High HiPerClockS™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can

CBTU4411EE

Abstract: HP10 JESD22-A114 JESD22-A115 JESD78 001A 2dp1
Contextual Info: CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 03 — 12 October 2009 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin HPn is multiplexed to one of four DIMM port pins (xDPn). The

Contextual Info: PRELIMINARY ICS83840B Integrated Circuit Systems, Inc. DDR SDRAM MUX GENERAL DESCRIPTION FEATURES The ICS83840B is a DDR SDRAM MUX and is ICS a member of the HiPerClockS family of High HiPerClockS™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can

"differential input" common mode voltage LVDS

Abstract: JESD78B
Contextual Info: 2DP1502 1:2 LVPECL Fanout Buffer 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, HCSL, or CML input pair distributed to two LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input

JESD78B

Contextual Info: 2DP1502 1:2 LVPECL Fanout Buffer Features Functional Description • One differential LVPECL, LVDS, or CML input pair distributed to two LVPECL output pairs ■ 20-ps maximum output-to-output skew ■ 480-ps maximum propagation delay ■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz

hp8k

Abstract: 1DP6 4318C CBTV4010 ICS83840 ICS83840AH ICS83840AHT 2dp3
Contextual Info: ICS83840 Integrated Circuit Systems, Inc. DDR SDRAM MUX GENERAL DESCRIPTION FEATURES The ICS83840 is a DDR SDRAM MUX and is a member of the HiPerClockS family of High PerforHiPerClockS mance Clock Solutions from ICS. The device has 10 Host Lines and each host line can be passed to 4