27559 Search Results

bzx 850

Abstract: bzx 850 30
Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

2N3725

Abstract: complement to 2n3700 2N3253 TA100-F FTS03904 curve set t144 2N3700 2N3724 test 2N3700 tl 4013
Contextual Info: FAIRCHILD SEMICONDUCTOR _ A4 _ DE §341^1,74 GOSTSSl 3 FAIRCHILD 2N3253 A Schlumberger Company NPN Switching Type ABSOLUTE MAXIMUM RATINGS Note 1 Temperatures Storage Temperature -65° C to 200° C Operating Junction Temperature 200° C Power Dissipation (Notes 2 & 3)

CY7C1470BV33

Contextual Info: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

2755-NC43

Abstract: led matrix projects topics Allen-Bradley SLC MTBF 1787-MGR MTBF calculation excel slc 500 database to excel "cyclic timer" 2755-nc48 DF1 PROTOCOL led message display projects
Contextual Info: Allen-Bradley AdaptaScan Software Cat. No. 2755-ASN User Manual Important User Information Solid state equipment has operational characteristics differing from those of electromechanical equipment. “Safety Guidelines for the Application, Installation and Maintenance of Solid State Controls” (Publication SGI-1.1)

Contextual Info: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

Contextual Info: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

SKIIP 33 nec 125 t2

Abstract: skiip 613 gb 123 ct RBS 6302 ericsson SKIIP 513 gb 173 ct THERMISTOR ml TDK 150M pioneer PAL 010a Project Report of smoke alarm using IC 555 doc SKiip 83 EC 125 T1 ericsson RBS 6000 series INSTALLATION MANUAL Ericsson Installation guide for RBS 6302
Contextual Info: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.

lm 8446

Abstract: FIN-02231 IR-58001 mt 6680 76S722333
Contextual Info: SAMSUNG SEMICONDUCTOR SALES OFFICE-U.SA Northwest North Central Northeast 3655 North First Street San Jose, CA 95134 TEL: 408-544-4000 FAX : 408-544-4934 1111 Ptaza Drive, Suite 100 Schaumburg, IL 60173 TEL : 847-969-9515 FAX : 847-969-9509 238 Littleton Road. Suite 201

W157

Abstract: mn 6912 bc 5578 Nanjing Micro One Electronics
Contextual Info: SAMSUNG SEMICONDUCTOR SALES OFFICE-U.SA Northwest North Central Northeast 3655 North First Street San Jose, CA 95134 TEL : 408-954-7000 FAX : 408-954-7883 300 Park Boulevard, Suite #210 Itasca, IL 60143-2636 TEL : 630-775-1050 FAX : 630-775-1058 238 Littleton Rd. Suite 201

Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Contextual Info: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces 

CY7C1312BV18

Abstract: CY7C1314BV18 CY7C1312
Contextual Info: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

Hyde Park Electronics

Abstract: 4001 PA PIONEER
Contextual Info: /AN Ü ^ Sales Offices, Distributors & Representatives September 1991 Altera U.S. Sales Offices N O R TH ER N C A LIFORNIA C O R PO R A TE H EAD Q U A R TER S Altera Corporation 2610 Orchard Parkway San Jose, C A 95134-2020 TEL: (408) 984-2800 FAX: (408) 248-7097

telemecanique magnetic contactor

Abstract: V40h merlin gerin DC 24V double POLE MCB NC100LMA IEC 60898 category C Merlin Gerin shunt trip mx Multi 9 C60HD Merlin Gerin c60hb merlin gerin multi 9 C60HD merlin gerin rcbo
Contextual Info: Contents Axiom MCB’s features and benefits C60 features and benefits Axiom MCB outgoers C60 MCB outgoers MCB auxiliaries MCB accessories DPN MCB’s NC100 MCB NC100 auxiliaries NC100 accessories NC100LMA P25M P25M accessories P25M auxiliaries 41 42 44-45

Contextual Info: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

Contextual Info: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses

CY7C1312BV18-167BZC

Contextual Info: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth

3M Touch Systems

Contextual Info: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■

CY7C1470BV33

Abstract: CY7C1472BV33 CY7C1474BV33
Contextual Info: CY7C1470BV33 CY7C1472BV33, CY7C1474BV33 72 Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250 MHz bus operations with zero wait states

CY7C1418AV18

Abstract: CY7C1420AV18
Contextual Info: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

STR 50115

Abstract: STR 50115 A 307-1B Sp 9685 94V-0 SR-01 golden
Contextual Info: •Mirsï 1 K A T 'L H O U S IK G :S iIU B i£ O W iT 4 3 « tS H E m i3 7 Of 7 7 .K X l‘CGOLO WlftOPHOSPHCW BfiOKZt, ALLOY UKS CSIOOO. PLk^lHGOtO^fXnfa/£R 2.S 3 * 100JU*Hi., Cg $PPOXt^f> INSULATED WIRE: ' ' STYLE A: 27 AWG. 7 STRANDS OF TINNED COPPER VIRE. P VC INSULATION.

Contextual Info: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™

atmel 720 24c32

Abstract: atmel 24c04 ISO7816-UART saa 1097 PHILIPS A004 nds ATMEL 24c64 Atmel 24C08 ATMEL 24c32 atmel 24c16 BTA 16 6008
Contextual Info: PNX8526 User Manual UM10104_1 Programmable Source Decoder with Integrated Peripherals Rev. 01 — 8 October 2003 Revision History: Version Date Document Status Author s 01 8 October 2003 First release Stephen Hibberd PNX8526 Philips Semiconductors Programmable Source Decoder with Integrated Peripherals

Contextual Info: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces