256TBB2 Search Results

27C010-70

Abstract: 1N3064 27C010 C0104 CY27C010
Contextual Info: W r* CYPRESS Features ADVANCED INFORMATION 128K X 8 CMOS EPROM Functional Description • CMOS for optimum speed/power • High speed — — 70 ns max. • Low power — 220 mW max. — Less than 85 mW when deselected • Byte-wide memory organization • 1 0 0 % reprogrammable in the

TDA 11106

Abstract: ami bios 486dx vesa local bus ldev intel 486SL 82c596 am486 Block Diagram AMI bios power management E5EF 486 system bus 486dx isa bios
Contextual Info: PRELIMINARY C Y PR E SS Features • Provides an interface between the PCI Local Bus and the CPU bus • PCI Bus Rev. 2.0 compliant • Supports Intel 486DX, 486DX2, 486SX, 486SL, P24T, AMD AM486 and Cyrix Cx486S2 M6/M7 CPUs • Interfaces with Cypress CY82C596 or

Contextual Info: Features • Multiple clock outputs to meet re­ quirements of OPTi Viper chipset — Five CPU clocks @ 66.66 MHz, 60 MHz, and 50 MHz, pin selectable — One Early clock, leads CPU clocks by 2 to 5 ns — Six PCI clocks CPUCLK/2 — Two Ref. clocks @ 14318 MHz

Contextual Info: 32K x 9 Static RAM Features Functional Description • High speed — 20 ns The CY7C188 is a high-performance CMOS static RAM organized as 32,768 words by 9 bits. Easy memory expansion is provided by an active-LOW chip enable CEi , an active-HIGHchip enable (CE 2 ),

Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features • Provides control for the cache, system memory, and the PCI bus • PCI Bus Rev. 2.1 compliant • Supports 3V Pentium™, AMD K5, K6, and Cyrix 6x86 M1 CPUs • Support for WB or WT L1 cache

Contextual Info: CY7C460 CY7C462 CY7C464 m f C Y PR ESS Features Cascadable 8K x 9 FIFO Cascadable 16Kx 9 FIFO Cascadable 3 2 K x 9 F IF O Functional Description d ata outputs go to the high-im pedance state w hen R is H IG H . T he CY7C460, CY7C462, and CY7C464 . A H alf Full H F output flag is provided

n20s

Abstract: CY7C9700-NC PIO-12 Repeater rf unmanaged repeater 100BASE-FX CY7C9700 CY7C9701 0C220
Contextual Info: Fast Ethernet Repeater Controller • Repeater loopback mode for testing Features • 13 Port IEEE 802.3u compliant 100BASE-T Repeater Controller • Serial EEPROM interface supports custom repeater configurations • 13 General purpose programmable I/O pins

cl96

Abstract: D-5200 7C196 A12C CY7C194 CY7C195 CY7C1-95 CY7C196 Cypress 7c194 ZP10
Contextual Info: CY7C194 CY7C195 CY7C196 *0 C Y PR ESS 64K x 4 Static RAM Features Functional Description • High speed — 12 ns • Output enable OE feature (7C195 and 7C196) • CMOS for optimum speed/power • Low active power — 880 mW • Low standby power — 220 mW

Contextual Info: CY7C383A CY7C384A *= CYPRESS Very High Speed 2K 6K Gate CMOS FPGA — Fast, fully autom atic place and route — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of

C3816

Contextual Info: IIIWI IdlllW. IVIUMUdy, MUyU£>l I / , \ W £ Revision: Wednesday, March 16,1994 CY7C381 CY7C382 W CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays