16L2 Search Results

16LB

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - AND LOGIC - ARRAY - - n > ID E E 10L8/-2 E E E E - AND - I H > ID

Contextual Info: Devices 20-P in 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16L8-25

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16c1

Abstract: 14H4-2
Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3

16l8

Abstract: 16x4 HAL 16L8 MONOLITHIC MEMORIES 16L8-25 16R8
Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16L8-25

Abstract: 16l8 910U 16r8
Contextual Info: Devices 20-P in 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16L8A-4

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - - ID E E 10L8/-2 - AND - ARRAY - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE 16R8/B/B-2/B-4

16L8B-2

Abstract: 16R6B2
Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - AND LOGIC - ARRAY - - n > ID E E 10L8/-2 E E E E - AND - I H > ID

16L8B-4

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - - ID E E 10L8/-2 - AND - ARRAY - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3

16L8A-2

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE 16R8/B/B-2/B-4

12L6-2

Abstract: 12H6-2
Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E - E = £> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - AND LOGIC - ARRAY - E 10L8/-2 E E E E - AND - ARRAY - E

16RP4A

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - - ID E E 10L8/-2 - AND - ARRAY - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3

Contextual Info: TICPAL18V8-30M, TICPAL18V8 25C ADVANCED EPICm CMOS GENERIC M i D 3 0 8 7 . DECEMBER 1 9 8 7 • 20-Pin Advanced C M OS Generic PAL •

16V8

Abstract: GAL16LV8 GAL16LV8C GAL16LV8C-10LJ GAL16LV8C-15LJ GAL16LV8C-7LJ GAL16LV8D GAL16LV8D-3LJ GAL16LV8D-5LJ
Contextual Info: ree Lead-Fage P a c k ns Optio le! b Availa Features GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output

AM 16v8

Abstract: palce16v8 programming algorithm PALCE erase AMD PALCE PALCE Programmer palce programming algorithm
Contextual Info: F IN A L COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family AdvaM n,“ o EE CMOS 20-Pin Universal Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

palce16V8 programming

Abstract: AMD palce16v8 programming palce16v8h20 PALCE16V8Q-25PC palce16v8 programming guide
Contextual Info: _ COM’L: H-10/15/25, Q-15/25 MIL: H-20/25 Cl Advanced Micro Devices PALCE16V8 EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pln GAL devices ■ Electrically erasable CMOS technology

uart 16c850

Abstract: 16C550 XR16L784 XR16L784CV XR16L784IV
Contextual Info: XR16L784 xr HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART OCTOBER 2005 REV. 1.2.2 GENERAL DESCRIPTION FEATURES The XR16L7841 784 is a quad Universal Asynchronous Receiver and Transmitter (UART). The device is designed for high bandwidth requirement in communication systems. The global interrupt source

ST16C650A

Abstract: 16C450 16C550 ST16C450 ST16C550 ST16C580 TL16C750 XR16C850 16C650A 2083m
Contextual Info: XR16C850 xr 2.97V TO 5.5V UART WITH 128-BYTE FIFO AUGUST 2005 REV. 2.3.1 GENERAL DESCRIPTION FEATURES The XR16C8501 850 is a Universal Asynchronous Receiver and Transmitter (UART). This device supports Intel and PC mode data bus interface and is software compatible to industry standard 16C450,

14L4

Abstract: 10l8 12L6 12H6 16c1 4511 logic diagram 1117 L schematic diagram PAL14L pin shourd PAL10H8
Contextual Info: ADV MICRO PLA/PL E/ ARR AY S =ib U2 b7526 ADV MICRO P L A / P L E / ARRAYS D E | 055755b 0057114 7 96D 27114 D T-V6-/3-V7 Combinatorial PALI 0H8 Series 1 0 H 8 , 1 2 H 6 , 1 4 H 4 , 1 6 H 2 1 6 C 1 1 0 L 8 , 1 2 L 6 , 1 4 L 4 - , 1 6 L 2 Ordering Information

Contextual Info: Commercial INC. PEEL 16V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features • Compatible with Popular 16V8 Devices — 16V8 socket and function compatible — Programs with standard 16V8 JEDEC file — 20-pin DIP, SOIC, and PLCC packages

GAL16VB

Abstract: National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm
Contextual Info: GAL16V8 National Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

XR16C8641

Abstract: EXAR MARKING CODE intel date code marking qfp100
Contextual Info: XR16C864 -Quad UART with RX/TX FIFO Counters and 128-Byte FIFO HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XR16C864 Support Info Request How to Order Samples How to Buy Print this page Quad UART with RX/TX FIFO Counters and 128-Byte FIFO