12L6 Search Results

25L6-GT

Abstract: 50L6-GT 12L6-GT 25L6GT 50L6GT 12L6GT tube 12L6 50L6gt tube pentode 12L6
Contextual Info: 25L6-GT 12L6-GT 5 0 L6 -G T 25L6-GT - 1 2L6-GT - 50 L6-GT BEAM PENTODE ggectffc* ET-T867 Page 1 For AF Pow er Amplifier A pplications TUBES 7-54 — = DESCRIPTION A N D RATING^ The 25L6-GT is a beam pentode designed for use in the audio-frequency power output stage of radio and television receivers. Features include high

Contextual Info: TICPAL18V8-30M, TICPAL18V8 25C ADVANCED EPICm CMOS GENERIC M i D 3 0 8 7 . DECEMBER 1 9 8 7 • 20-Pin Advanced C M OS Generic PAL •

16V8

Abstract: GAL16LV8 GAL16LV8C GAL16LV8C-10LJ GAL16LV8C-15LJ GAL16LV8C-7LJ GAL16LV8D GAL16LV8D-3LJ GAL16LV8D-5LJ
Contextual Info: ree Lead-Fage P a c k ns Optio le! b Availa Features GAL16LV8 Low Voltage E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output

C57401AJ

Abstract: C57401J/883B M38510 numbering C57402AJ AMD - C57401J MMI PAL14L8 5962-8779105EX 53RA1681 C57401L
Contextual Info: M ilitary Specialty Memory Whatever your military data buffering needs, Advanced Micro Devices has the right specialty memory device to fit your applica­ tion. All of our military bipolar and CMOS First-in First-out FIFO memories are fully screened to MIL-STD-883.

AM 16v8

Abstract: palce16v8 programming algorithm PALCE erase AMD PALCE PALCE Programmer palce programming algorithm
Contextual Info: F IN A L COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family AdvaM n,“ o EE CMOS 20-Pin Universal Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity

palce16V8 programming

Abstract: AMD palce16v8 programming palce16v8h20 PALCE16V8Q-25PC palce16v8 programming guide
Contextual Info: _ COM’L: H-10/15/25, Q-15/25 MIL: H-20/25 Cl Advanced Micro Devices PALCE16V8 EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pln GAL devices ■ Electrically erasable CMOS technology

14L4

Abstract: 10l8 12L6 12H6 16c1 4511 logic diagram 1117 L schematic diagram PAL14L pin shourd PAL10H8
Contextual Info: ADV MICRO PLA/PL E/ ARR AY S =ib U2 b7526 ADV MICRO P L A / P L E / ARRAYS D E | 055755b 0057114 7 96D 27114 D T-V6-/3-V7 Combinatorial PALI 0H8 Series 1 0 H 8 , 1 2 H 6 , 1 4 H 4 , 1 6 H 2 1 6 C 1 1 0 L 8 , 1 2 L 6 , 1 4 L 4 - , 1 6 L 2 Ordering Information

Contextual Info: Commercial INC. PEEL 16V8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Features • Compatible with Popular 16V8 Devices — 16V8 socket and function compatible — Programs with standard 16V8 JEDEC file — 20-pin DIP, SOIC, and PLCC packages

GAL16VB

Abstract: National SEMICONDUCTOR GAL16V8 GAL16V8 application notes GAL16v8 algorithm
Contextual Info: GAL16V8 National Semiconductor GAL16V8 Generic Array Logic General Description Features The NSC E2CMOS GAL device combines a high per­ formance CMOS process with electrically erasable floating gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

16v8h

Abstract: 16V8Q palce16v8 programming algorithm 16v8z PAL16C1 PAL16R8 PALCE16V8 PALCE16V8Z 16V8H-10 16v8z-25
Contextual Info: PALCE16V8 PALCE16V8Z COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/25, Q-20/25 COM’L:-25 IND:-12/15/25 PALCE16V8 and PALCE16V8Z Families EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Pin and function compatible with all 20-pin PAL devices

Contextual Info: AT18V8Z Features • 20-pin Universal EPLD • Virtually Zero Standby Power • Functional Replacement for Common 20-Pin Programmable Devices Io l = 24 mA • High Performance CMOS EPROM Cell Technology Erasable Reconfigurable 100% Testable • 25 ns and 35 ns Max Propagation Delay Commercial

hy18cv8s

Abstract: low cost eeprom programmer circuit diagram altera EP300 Altera ep310 EP300 HYUNDAI i10 10L8 16H8 HY18CV8 R1-48-*-F
Contextual Info: AL HY18CV8 HYUNDAI SEMICONDUCTOR CMOS EEPLD DESCRIPTION FEATURES T he H Y 18CV8 is a CM O S E lectrically E ra sa­ ble P rogram m able Logic Device E E P L D th at provides a high perform ance; low power, re­ program m able and architecturally flexible alter­

Contextual Info: COM’L: -25 IND: -25 a P A L C E 1 6 V 8 Z -2 5 Zero-Power 20-Pin EE CMOS Universal Programmable Array Logic_ DISTINCTIVE CHARACTERISTICS Advanced Micro Devices • Outputs programmable as registered or combinatorial in any combination ■ Programmable output polarity

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

16LB

Contextual Info: Devices 20-Pin 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 bjl=jl£jl£jl=jl£jl=jyi=iy 14H4/-2 12H6/-2 10H8/-2 E E E - AND LOGIC ARRAY E =£> = 0 Ed e = t> =T> i > ID E H > ID E =0 - - AND LOGIC - ARRAY - - n > ID E E 10L8/-2 E E E E - AND - I H > ID

GAL16V8

Abstract: IC gal16v8 gal16v8b-10lj 16v8b GAL programmer schematic gal16v8 programming 16V8 GAL16V8B-7LJ GAL16V8B-7LP GAL16V8C
Contextual Info: Specifications GAL16V8 GAL16V8 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES 2 • HIGH PERFORMANCE E CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 166 MHz — 4 ns Maximum from Clock Input to Data Output

Contextual Info: Devices 20-P in 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16L8-25

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

16l8

Abstract: 16x4
Contextual Info: Devices 20-Pin E E- =£> = 0 Ed e =L> = t> AND = T > AND = E > LOGIC LOGIC ARRAY i > ID E - ARRAY = £ > E H > ID E =E> - =0 - - n > ID E E 10L8/-2 H > I ID ID =E> - AND = E > 3 - ARRAY ID =E> 3 E =E> 3 = T > ID "I 3 EE EErr> AND E - LOGIC = E > ARRAY E = [>

Contextual Info: Devices 20-Pin 14H4/-2 12H6/-2 10H8/-2 16H2/-2 16C1/-2 16L2/-2 16L8/B/B-2/B-4 A/A-2/A-4 - AND LOGIC ARRAY E - E =£> = 0 Ed = t> =T> i > ID H > ID =0 n > ID e E E - - - AND - ARRAY - E - I H > ID ID =E> =E> 3 ID =E> 3 =E> 3 = T > ID 3 "I EE EEEE EE EE r t

EP320

Abstract: altera ep320 EP320-2 program altera ep320 EP320I RAL16L8 EP3201 PAL16LB Eprom, altera, ep320 cx 1213 circuit diagram
Contextual Info: § /à\^ 8 M ACR O CELL EPLD EP320 FEATURES GENERAL DESCRIPTION • User-Configurable replacement for TTL, 74HC and 20 pin PAL Family. The Altera EP320 Erasable Programmable Logic Device may be used as a replacement for T TL and 74HC. It also provides a high speed, low power “plug

palce16v8 programming algorithm

Abstract: AMD palce16v8 programming palce16v8 programming guide palce16v8z pal16r8 programming algorithm APL DOC SIC jmd PROGRAMMER PAL16R8 algorithm amd palce programming Guide palce16v6
Contextual Info: COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 a MIL: H-15/20/25 Advanced Micro Devices PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Pin, function and fuse-map compatible with all 20-pin GAL devices

PLDC18G8

Abstract: T1216 416rp Cypress 12h6 16v8 programming 15WC
Contextual Info: PLDC18G8 CYPRESS SEMICONDUCTOR CMOS Generic 20-Pin Programmable Logic Device • Generic architecture to replace >tandard logic functions including; 10H8, 1 2 H 6 ,1 4 H 4 ,1 6 H 2 ,1 0 L 8 ,1 2 U , 14L4, 1 6 L 2 ,1 0 P 8 ,1 2 P 6,14P 4,1«P 2,16H 8, 16L 8,16P 8,16R 8,16R 6,16R 4,16R P 8,

P320S

Abstract: F16V8BQ 16v8b pld program 16R8
Contextual Info: Features * Industry Standard Architecture - Emulates Many 20-pin PALs - Low-cost Easy-to-use Software Tools * High-speed Electrically-erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay * Several Power Saving Options Device lcc, Standby