15WC Search Results

74151

Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Contextual Info: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of

C3402

Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Contextual Info: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

Contextual Info: CY7C344 CY7C344B W w CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

8ohm .5W speaker

Abstract: 15w audio amplifier circuit diagram YDA143-EZ YDA143 YDA*143 12v power amplifiers DIGITAL AUDIO POWER AMPLIFIER digital amplifier Leaded ceramic multilayer capacitors General Da POWER AMPLIFIER CIRCUIT DIAGRAM 10000
Contextual Info: YDA143 D- 3M STEREO 15W DIGITAL AUDIO POWER AMPLIFIER •Overview YDA143 D-3M is a high efficient digital audio power amplifier IC that operates with a single 12V power supply. An audio power amplifier with a maximum output of 15W (RL=4Ω)x2ch can be configured with one chip.

20G10-25

Abstract: 20G10-30 20G10B-20 20G10B-25 12L10 16L6 18L4 20L10 20L8 20G108
Contextual Info: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Fully AC and DC tested

PLDC18G8

Abstract: T1216 416rp Cypress 12h6 16v8 programming 15WC
Contextual Info: PLDC18G8 CYPRESS SEMICONDUCTOR CMOS Generic 20-Pin Programmable Logic Device • Generic architecture to replace >tandard logic functions including; 10H8, 1 2 H 6 ,1 4 H 4 ,1 6 H 2 ,1 0 L 8 ,1 2 U , 14L4, 1 6 L 2 ,1 0 P 8 ,1 2 P 6,14P 4,1«P 2,16H 8, 16L 8,16P 8,16R 8,16R 6,16R 4,16R P 8,

Contextual Info: y PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

cy7C344

Abstract: C3M11
Contextual Info: / 9 / I J/ 3 1 Revision: Friday, Apni IS, 1934 CY7C344 f ß CYPRESS i 32-Macrocell MAX FPT P Features Functional Description • High-performance, higfa-deiislty re­ placement for TTL, 74HC, and cus­ tom logic Available in a 28-pin 300-mil DIP or •win­

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

12L10

Abstract: 16L6 20L10 20L8 PLDC20G10 PLDC20G10B ULTRA37000
Contextual Info: PLDC20G10B PLDC20G10 USE ULTRA37000 FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns

20G10

Abstract: 20G10B-20 12L10 16L6 18L4 20L10 20L8
Contextual Info: fax id: 6014 1P LDC20 G1 0B/P LD C20 G1 0 PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable — Uses proven EPROM technology • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns

Contextual Info: CY7C332 ¡W CYPRESS SEMICONDUCTOR 13 in p u t m acrocells, each having: — C om plem entary input — R egister, latch, o r tra n s p a re n t access — Two clock sources Features • • Registered Combinatorial EPLD 12 I/O m acrocells each having: — R egistered, latched, o r tra n s p a re n t

Contextual Info: PALC22V10B CYPRESS SEMICONDUCTOR • Advanced second generation PAL ar­ chitecture • Low power — 90 mA max. standard — 100 mA max. military Functional Description — “15” and “20” military 10/15 ns tc o 10/17 ns ts 15/20 ns tpo 50/31 MHz Up to 22 input terms and 10 outputs

c258

Abstract: CERAMIC LEADLESS CHIP CARRIER h67 YW PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC
Contextual Info: CY7C258 CY7C259 CYPRESS 2Kx 16 Reprogrammable State Machine PROM Features Functional Description • High speed: 100-MHz operation T h e CY7C258 and CY7C259 a re 2K x 16 C M O S P R O M s specifically designed for use in state m achine applications. — tc p — 10 ns

Contextual Info: UNCONTROLLED DOCUMENT 11,“35 [0.470] CAUTION: STATIC SENSITIVE DEVICE FOLLOW PROPER E.S.D. HANDLING PROCEDURES WHEN WORKING WITH THIS PART. REV, A PANEL CUTOUT PART NUMBER REV. SS —LXMP501 1 SWC A E.C.N. NUMBER AND REVISION COMMENTS E.C.N. #10809. & REDRAWN IN 3D.

74151 PIN DIAGRAM

Abstract: 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C340 CY7C341B CY7C342B
Contextual Info: 40 EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase

Contextual Info: CY7C332 CYPRESS Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product term s (PTs) per output — Product term (PT) output polarity

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR Features 2K x 16 Reprogrammable State Machine PROM Functional Description The CY7C258 and CY7C259 are 2K x 16 CMOS PROMS specifically designed for — tcp = 12 ns use in state machine applications. — tcKO = 9 ns State machines are one of the most com­

Contextual Info: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output

IN5456A

Abstract: IN5456 IN5448A 1N5446ARL 1N5448ARL 1N5456A IN5446 A200 REACH in5448
Contextual Info: — MOTORO~ SEMICONDUCTOR o TECHNICAL Silicon -ning Order this document by 1N5446ARUD DATA Diodes 1N5446ARL 1N5448ARL 1N5456A,., These are epitmial passivated abrupt junction tuning diodes designed for electronic tuning, FM, AFC and harmonic–generation

cp 9AA

Contextual Info: PRELIMINARY r v p p r Q c = SEMICONDUCTOR 2K x 16 Reprogrammable State Machine PROM Features F unctional D escription • High speed: 83-MHz operation T he CY 7C258 and CY 7C259 are 2 K x 16 C M O S PR O M S specifically designed fo r use in state m achine applications.

MI1600

Abstract: 100L AN569 MMDF4P03HD MMDF4P03HDR2 ldm # jl
Contextual Info: . MOTOROLA SEMICONDUCTOR TECHNICAL Order this document by MMDF4P03HDID DATA Advance Information MMDF4P03HD Medium Power Surface Mount Products Motorola TMOS Dual P-Channel FieBdEffect Transistors Dual HDTMOS devices are an advanced series of power MOSFETS which utilize Motorola’s

74HC

Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131
Contextual Info: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins