|
Contextual Info: CY7C4261V CY7C4271V PRELIMINARY 16Kx9 Low Voltage Deep Sync FIFO Speed ns 15 25 Ordering Code Package Name Package Type Operating Range CY7C4261V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial CY7C4261V-15JI J65 32-Lead Plastic Leaded Chip Carrier
|
Original
|
16kx9cy7c4261v-15jccy7c4261v-15jicy7c4261v-25jc+432-leadcy7c4261vcy7c4271v32kx9
|
PDF
|
7M206S120
Contextual Info: IDT7M205S IDT7M206S 8KX9&16KX9 CEMOS PARALLEL IN-OUT FIFO MODULE Integrated Device Technology» Inc. FEATURES: • • ■ • ■ • • • • • • First-In/First-Out memory module 8K x 9 organization IDT7M205S 16K x 9 organization (IDT7M206S)
|
OCR Scan
|
16kx9idt7m205sidt7m206sidt7m205s/206s+5idt7203idt7204205s/206s8k/16k7m206s120
|
PDF
|
HF receiver
Abstract: ANM051 M672
Contextual Info: ANM051 TSS923 & TSS933 HSDLink with FIFO Using Asynchronous FIFO This note describes the design considerations of a high-speed serial transmitter TSS923 / receiver (TSS933) with FIFO (First In First Out) data buffers. Transmitter interface The transmitter interface consists of a new single 16Kx9 M67206-12 interfacing directly to the HSDLink
|
Original
|
anm051tss923tss93316kx9+3m67206-12hf receiverm672
|
PDF
|
TEMIC PLD
Abstract: ANM051 M67206
Contextual Info: ANM051 TSS923 & TSS933 HSDLink with FIFO 1. Using Asynchronous FIFO This note describes the design considerations of a high–speed serial transmitter TSS923 / receiver (TSS933) with FIFO (First In First Out) data buffers. 1.1. Transmitter interface The transmitter interface consists of a new single 16Kx9
|
Original
|
anm051tss923tss93316kx9+2m67206temic pld
|
PDF
|
CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
|
Original
|
cy7c4255v/cy7c4265vcy7c4275v/cy7c4285v8k/16k/32k/64kx18cy7c4255/65/75/85v+5cy7c42x5vcy7c4255vcy7c4265vcy7c4275vcy7c4285v
|
PDF
|
|
Contextual Info: HIGH-SPEED 1 6 K X 9 DUAL-PORT STATIC RAM ID T 7 0 1 6 S /L Features using the Master/Slave select when cascading more than * True Dual-Ported memory cells which allow sim ultaneous one d e v i c e _ reads of the sam e memory location M/S = V ih for B U S Y output flag on Master
|
OCR Scan
|
20125135ns12/15/20/25/35nsidt7016s750mw+2idt70161-68-pin
|
PDF
|
CY7C4261
Abstract: CY7C4271 CY7C4271-15LMB IDT72201 n25l
Contextual Info: fax id: 5412 - CY7C4261 V CYPRESS CY7C4= 16K/32Kx9 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 16K x 9 (CY7C4261) • 32K x 9 (CY7C4271) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle
|
OCR Scan
|
cy7c4261cy7c4271100-mhzcy7c4271-15lmb+332-pinidt72201n25l
|
PDF
|
CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC QO-17
Contextual Info: CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V V CYPRESS 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfac es. All are 18 bits wide and are pin/functionally compatible to
|
OCR Scan
|
cy7c4255v/cy7c4265vcy7c4275v/cy7c4285v32k/64kxcy7c4255v+8cy7c4265vcy7c4275vcy7c4285v100-mhz10-nscy7c42x5vcy7c42x5v-ascqo-17
|
PDF
|
723653
Abstract: 72V7290 72V3613 72V7250 72V3611 72V3623 72V72100 72V7230 72V7240 72V7260
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. July’00 IDT FIFO Memory Products Quick Reference Guide
|
Original
|
512-bit16k-bit64k-bit128k-bit+14256k-bit512k-bit100mhz133mhz72365372v729072v361372v725072v361172v362372v7210072v723072v724072v7260
|
PDF
|
723653
Abstract: BI 7284 72V7250 72V72100 72V7230 72V7240 72V7260 72V7270 72V7280 72V7290
Contextual Info: Selector Guide for FIFO Memory Products • Synchronous FIFOs SuperSync II, SuperSync™ SyncFIFO™, DualSync™ • Bi-Directional Synchronous FIFOs • Asynchronous FIFOs the leading provider of FIFO memories. Jan’00 IDT FIFO Memory Products Quick Reference Guide
|
Original
|
512-bit16k-bit64k-bit128k-bit+12512k-bit7236x3/72v36x3723653bi 728472v725072v7210072v723072v724072v726072v727072v728072v7290
|
PDF
|
|
Contextual Info: 2.5 VOLT HIGH-SPEED TeraSync FIFO IDT72T1845, IDT72T1855 18-BIT/9-BIT CONFIGURATIONS IDT72T1865, IDT72T1875 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, IDT72T1885, IDT72T1895 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
|
Original
|
idt72t1845idt72t185518-bit/9-bitidt72t1865+6idt72t1875idt72t1885idt72t1895idt72t18105idt72t18115idt72t18125
|
PDF
|
A12L
Abstract: A13L IDT7016 IDT7016L IDT7016S
Contextual Info: HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35ns max. – Commercial:12/15/20/25/35ns (max.) Low-power operation
|
Original
|
20/25/35ns12/15/20/25/35nsidt7016s750mw+5idt7016lidt7016idt7016s/la12la13l
|
PDF
|
add round key for aes algorithm
Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
add round key for aes algorithmdetail of half adder icdin 54632-bit half adder+6handbook texas instrumentsic to design 2 by 2 binary multiplierse 135 pin configurationverilog code for twiddle factor romtransistor c789 6aep3sl1501152
|
PDF
|
SECDED
Abstract: EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),
|
Original
|
siii51004-1320-bit144-kbitm144k+2secdedep3se50
|
PDF
|
|
|
IDT7014
Abstract: IDT7015
Contextual Info: N E W S R E L E A S E FOR IMMEDIATE RELEASE FOR FURTHER INFORMATION: Julie Cline, Public Relations Specialist Carl May, SMP Marketing Manager 408 654-6464 (408) 754-4623 IDT EXPANDS X9 FAMILY WITH INDUSTRY’S FASTEST DUAL-PORT MEMORIES 12ns Dual-Ports Support Growing Demand for Fast DSP Systems
|
Original
|
idt701516kx980mhzidt7014 |
PDF
|
ken2
Contextual Info: fax id: 5421 •■■■■■■'■jH/m'r. a S S K , : CY7C4261V CY7C4271V 'S^i,„*$ & :*■ _ . " T jjjl? 16K/32Kx9 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems
|
OCR Scan
|
cy7c4261vcy7c4271v16k/32kx967-mhz+1ken2
|
PDF
|
a32 smd
Contextual Info: fax id: 5412 '•'■'■'■'■'■'■‘JJSt>iW.-. a S S K , : CY7C4261 CY7C4271 'S^ì,„*$ & :*■ _ jg ? . "T 16K/32Kx9 Deep Sync FIFOs Features Functional Description High-speed, low-power, first-in first-out FIFO memories 16K x 9 (CY7C4261)
|
OCR Scan
|
cy7c4261cy7c427116k/32kx9100-mhz+1a32 smd
|
PDF
|
|
Contextual Info: fax id: 5423 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 16K/32K/64K/128Kx9 Low Voltage Deep Sync FIFOs Features Functional Description 3.3V operation for low power consumption and easy integration into low voltage systems High-speed, low-power, first-in first-out FIFO
|
OCR Scan
|
cy7c4261v/cy7c4271vcy7c4281v/cy7c4291v16k/32k/64k/128kx9cy7c4261v+5cy7c4271vcy7c4281vcy7c4291v35-micron67-mhz
|
PDF
|
|
Contextual Info: HIGH-SPEED 16K x 9 DUAL-PORT PRELIMINARY IDT7016S/L STATIC RAM Integrated Device Technology, Inc. FEATURES: • True Dual-Ported m em ory cells which allow simulta neous reads of the sam e m em ory location • High-speed access — Military: 2 0 /2 5 /3 5 n s m ax.
|
OCR Scan
|
idt7016s/l12/15/20/25/35nsidt70161activeidt7016+5ma25771mil-std-88380-pin68-ping68-1
|
PDF
|
CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC
Contextual Info: CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems ■ High speed, low power, first-in first-out FIFO memories
|
Original
|
cy7c4255vcy7c4265vcy7c4275vcy7c4285v+432k/64kx18cy7c4255/65/75/85vcy7c42x5vcy7c42x5v-asc
|
PDF
|
CY7C4261
Abstract: CY7C4271 CY7C4271-15LMB
Contextual Info: CY7C4261, CY7C4271 16K/32K x 9 Deep Sync FIFOs Features Functional Description • High speed, low power, first-in first-out FIFO memories ■ 16K x 9 (CY7C4261) ■ 32K × 9 (CY7C4271) ■ 0.5 micron CMOS for optimum speed and power ■ High speed 100 MHz operation (10 ns read/write cycle times)
|
Original
|
cy7c4261cy7c427116k/32kcy7c4261/71+2cy7c42x1cy7c4271-15lmb
|
PDF
|
transistor 5503 dm
Abstract: hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.2 March 2011 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
ep3sl50ep3sl110ep3se80transistor 5503 dm+8hpc 3062power module si 3101 schematic diagramhybrid systems adc 560-3lsp 5503transistor horizontal c 5936ic transistor linear handbook4 pins jd 1803transistor si 6822
|
PDF
|
PMD 1000
Abstract: IC ax 2008 USB FM PLAYER ,national semiconductor Linear brief lb-3 EP4SGX230KF40 pin DIAGRAM OF DIP TOP 244 PN bc 1024 cq 724 g diode FM transmiter 10PIN fm recevier project report mbp schematic
Contextual Info: Stratix IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-2.0 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
|
Original
|
pmd 1000ic ax 2008 usb fm playernational semiconductor linear brief lb-3ep4sgx230kf40+6pin diagram of dip top 244 pnbc 1024cq 724 g diodefm transmiter 10pinfm recevier project reportmbp schematic
|
PDF
|
7142LA25L48B
Abstract: 7164L20 4Kx8 sram ttl 5962-8861011UA 7206l20l 5962-8855206YA 5962-8855206 5962-8953604 54FCT244AT 5962-8855206XA
Contextual Info: IDT Military Offerings FIFO Military Offerings Logic Military Offerings Multi-Port Military Offerings SRAM Military Offerings May 2005 FIFO Military Offerings FIFO Military Selector Guide by Part Number FIFO Military Selector Guide (by SMD Number) Obsolete Part List and Replacement Guide
|
Original
|
72401l10db72401l15db72401l25db72401l35db+1672403l10db72403l35db7200l20tdb7200l30tdb7201la20db7201la30db7142la25l48b7164l204kx8 sram ttl5962-8861011ua7206l20l5962-8855206ya5962-88552065962-895360454fct244at5962-8855206xa
|
PDF
|