144KBIT Search Results

br b2d

Contextual Info: SGS-THOMSON S ID - jx W : S /T IN T E R F A C E ST5420 D E V IC E W IT H M IC R O W IR E /D S I A D VA N C E DATA SINGLE CHIP 4 WIRES 192 KBIT/S TRANS­ CEIVER, PROVIDES ALL CCITT 1.430 LAYER 1 FUNCTIONS ISDN BASIC ACCESS HANDLING 144KBIT/S 2B + D TRANSMISSION

T60407

Abstract: Pulse Transformer T60407 ST5481 TQFP48 LINE FEED ISDN RJ45 plug dimension spec "Hot Plug and Play"
Contextual Info: ST5481 L.O.U.I.S - LOW COST USB ISDN SOLUTION PRODUCT PREVIEW • COMMUNICATION DEVICE CLASS AND HARDWARE FEATURES VENDOR REQUESTS S/T ISDN Interface ■ SUPPORTS OSI LEVEL 1 IN CONFOR- ■ BUS OR SELF POWERED APPLICATION PIN PROGRAMMABLE MANCE WITH UIT-T I.430 FOR BASIC

Contextual Info: HIGH-SPEED 8 K x 18 DUAL-PORT STATIC RAM PRELIMINARY IDT7035S/L Features * * True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access - * ♦ Com m ercial: 15120ns max. Low-power operation - ♦ ♦ ♦ IDT7035S

Contextual Info: HIGH-SPEED 8 K x 18 DUAL-PORT STATIC RAM PRELIMINARY IDT7035S/L I n t e g r a te d D e v iz e T e c h n o lo g y , l i e . FEATURES: • True Dual-Ported m em ory cells which allow sim ulta­ neous reads of the sam e m em ory location • H igh-speed access

H6850

Abstract: PEF24911 24911H PEF24911H Q67233 PEF 24911 Q67230-H1234 Q67233-H1233
Contextual Info: P RODUCT B RIEF IEC4-Q PEF 24911 V2.1 DFE-Q & PEF 24902 V2.1 (AFE) ISDN Echocancellation Circuit 4-Channel for 2B1Q Line Code The widely used ISDN 4-channel chipset IEC4-Q consisting of the analog frontend PEB/F 24902 (AFE) and the digital frontend PEB/F 24911 (DFE-Q) has been

SICAN

Abstract: PEB3265 Common Mode Choke 85u0 PEF 4265 PEF 80912 SAFETY AWT 1 11 C513 PEB2023 PEF81902
Contextual Info: Da ta S h ee t, D S 1, N ov . 20 01 T - S M I NT I X 4B3 T S e co n d G e n . M od ul ar I S D N N T I nt e ll ige n t e X t e nd e d PEF 81902 Version 1.1 Wired C o m m u n i ca t i o n s N e v e r s t o p t h i n k i n g . Edition 2001-11-12 Published by Infineon Technologies AG,

PEB 4266 T V1.2

Abstract: convert 230V AC to 5V DC without transformer PEF 3304 BSP135 transformer from 230V AC to 5V DC 230v ac to -48v dc converter 230V AC to 5V DC ic CNY 42 optocoupler relay for controlling 230v ac using 5v dual falc
Contextual Info: ICs for Communications Intelligent Network Termination Solution Guide for Intelligent Network Termination HL Solution Guide 04.99 DS 1 Revision History: Current Version: 04.99 Previous Version: - Page Page in previous (in current Version Version) Subjects (major changes since last revision)

s53 optocoupler

Abstract: PEF82912 NTC Siemens m 822 PEF 2091 F V5.3 PEF 2091 N V5.3 PEF 4265 PEF80912 PEF80913 PEF81912 PEF81913
Contextual Info: Da t a Sh e e t , DS 1 , M a rc h 2001 Q-SMINT IX 2B1Q Second Gen. Modular ISDN NT Intelligent eXtended PEF 81912/81913 Version 1.3 Wi r ed Comm unic at io n s N e v e r s t o p t h i n k i n g . Edition March 2001 Published by Infineon Technologies AG,

Contextual Info: AN 307: Altera Design Flow for Xilinx Users AN-307-7.0 Application Note Introduction Designing for Altera Field Programmable Gate Array devices FPGAs is very similar, in concept and practice, to designing for Xilinx FPGAs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software

RAM SEU

Abstract: dsp radiation hard
Contextual Info: White Paper Robust SEU Mitigation With Stratix III FPGAs Introduction The benefits of FPGAs over ASICs become ever more compelling as rapid-process technology scaling and innovation provide ever-greater speed, density, and power improvements. However, along with technology scaling

add round key for aes algorithm

Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.1 July 2010 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

SECDED

Abstract: EP3SE50
Contextual Info: 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640- in ROM mode only or 320-bit memory logic array blocks (MLABs),

smd code book 9u

Abstract: ELIC - PEF 20550 siemens relay pins CL15 ST01 ST10 ST11 ST20 ST21 ST30
Contextual Info: ICs for Communications Quad ISDN 4B3T Echocanceller Digital Front End DFE-T V2.1 PEF 24901 Version 2.1 Product Overview 04.99 DS 2 PEF 24901 Revision History: Current Version: 04.99 Previous Version: 09.98 Page Page in previous (in current Version Version)

A12L

Abstract: A13L CY7C006 CY7C016 TSOP 48 memory arbitration scheme C0066
Contextual Info: with Sem, In t, Busy CY7C006 CY7C016 16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True dual-ported memory cells which allow simultaneous reads of the same memory location • 16K x 8 organization CY7C006 • 16K x 9 organization (CY7C016)

Contextual Info: 5^E basassi D gdoitgö tt? •■uovi MOSEL MS443 Jntelligent Dual Port Burst Memory PRELIMINARY MOSEL-VITELIC DESCRIPTION FEATURES High Performance Intelligent Memory optimized for fast burst read and burst write operations Compatible with the MOSEL MS441 Concurrent Write

mt 1389 fe

Abstract: P-TQFP-144 how to build stk 463 stk 462 audio amplifier circuit diagram 5P31
Contextual Info: D at a S h eet , D S 2, Feb. 20 0 1 C165UTAH Embedded C166 with USB, IOM-2 and HDLC Support Version 1.3 Wired Communications N e v e r s t o p t h i n k i n g . Edition 2001-02-23 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

EP3SL340F1517

Abstract: altera cyclone 3 handbook texas instruments HC335FF1152 HC325Ff DDR3 jedec diode handbook fbga Substrate design guidelines hc335 texas instruments handbook
Contextual Info: HardCopy III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com HC3_H5V1-3.2 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

altera cyclone 3 slice

Abstract: EP3SL70F780 RAMB36 RAMB18x2 DSP48Es Xilinx VIRTEX-5 RAMB18 Xilinx ISE Design Suite 9.2i
Contextual Info: White Paper Guidance for Accurately Benchmarking FPGAs Introduction This paper presents a rigorous methodology for accurately benchmarking the capabilities of an FPGA architecture. The goal of benchmarking is to compare the capabilities of one FPGA architecture versus another. Since the FPGA

TIMER FINDER TYPE 85.32

Abstract: tsmc design rule 40-nm FINDER TYPE 85.32 Texas Instruments Stratix IV EP4S series Power Ref Design 8 tap fir filter verilog FBP BGA
Contextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.4 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

transistor 5503 dm

Abstract: hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.2 March 2011 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

PMD 1000

Abstract: IC ax 2008 USB FM PLAYER ,national semiconductor Linear brief lb-3 EP4SGX230KF40 pin DIAGRAM OF DIP TOP 244 PN bc 1024 cq 724 g diode FM transmiter 10PIN fm recevier project report mbp schematic
Contextual Info: Stratix IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-2.0 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

hc335

Abstract: 1517P WF484
Contextual Info: 1. HardCopy III Device Family Overview HIII51001-3.1 Introduction This chapter provides an overview of features available in the HardCopy III device family. More details about these features can be found in their respective chapters. HardCopy III devices are Altera’s low-cost, high-performance, low-power ASICs with

Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.4 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

A1GK

Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SIII5V1-1.0 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and