RAMB18X2 Search Results

RAMB18X2 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
RAMB36 Abstract: RAMB18X2 virtex 4 vs spartan 3e 720P ITURBT601 Spartan 3E VHDL code Contextual Info: H.264 Deblocker Core v1.0 DS594 v1.0 May 15, 2007 Product Brief Features LogiCORE Facts Core Specifics • H.264/MPEG-4 Part 10 Baseline/Main/High Profiles at Level 4.2 1080 1968 LUTs, 1948 flops 9 RAMB18x2, 6 RAMB36 720P 1968 LUTs, 1946 flops 5 RAMB18x2, 6 RAMB36	Original	ds594 264/mpeg-4 ramb18x2 ramb36 +4virtex 4 vs spartan 3e 720p iturbt601 spartan 3e vhdl code	PDF
RAMB36E1 Abstract: RAMB16s spartan6 lx25 LX15-12 deinterlace RAM18E1 bob deinterlacer cpu 226 deinterlacer BT.656 Contextual Info: VDINT Basic BT.656 Video Deinterlacer IP Core This deinterlacer IP core converts a standard interlaced video stream to progressive video format for further processing or display. Extremely efficient, the deinterlacer core requires little area and transforms the video with practically no delay.	Original	480i/576i ramb36e1 ramb16s spartan6 lx25 +7lx15-12 deinterlace ram18e1 bob deinterlacer cpu 226 deinterlacer bt.656	PDF
altera cyclone 3 slice Abstract: EP3SL70F780 RAMB36 RAMB18x2 DSP48Es Xilinx VIRTEX-5 RAMB18 Xilinx ISE Design Suite 9.2i Contextual Info: White Paper Guidance for Accurately Benchmarking FPGAs Introduction This paper presents a rigorous methodology for accurately benchmarking the capabilities of an FPGA architecture. The goal of benchmarking is to compare the capabilities of one FPGA architecture versus another. Since the FPGA	Original	altera cyclone 3 slice ep3sl70f780 ramb36 ramb18x2 +4dsp48es xilinx virtex-5 ramb18 xilinx ise design suite 9.2i	PDF
ac108 Abstract: h264 encoder AC127 YUV400 JM CODE ac127 applications RAMB36 Transistor+TL+31+AC Contextual Info: - THIS IS A DISCONTINUED IP CORE 0 H.264 CABAC Encoder Core v1.0 DS603 v1.0 May 31, 2007 Advance Product Specification Features LogiCORE Facts • H.264/MPEG-4 Part 10 Main/High/High Ext. Profiles Level 4.2+ Core Specifics Virtex™-5, Virtex-4, Spartan™-3E	Original	ds603 264/mpeg-4 1080i 1080i/p +9ramb18x2 ramb36 ac108 h264 encoder ac127 yuv400 jm code ac127 applications transistor+tl+31+ac	PDF
RAMB36 Abstract: H.264 integer transform fpga 7831 8627 H.264 microsoft 1080p field pattern virtex 4 vs spartan 3e VHDL code motion 1080i Vs 1080p DS602 Contextual Info: H.264 CABAC Core v1.0 DS602 v1.0 May 15, 2007 Product Brief Features • H.264/MPEG-4 Part 10 Main/High/High Ext. Profiles Level 4.2+ LogiCORE Facts Core Specifics • Support for up to HD 1080i and 1080p/60 fps at 75 Mbps. Resources Used • Output stream is compliant with International	Original	ds602 264/mpeg-4 1080i 1080p/60 +141080i/p 720i/p 1080p/30 1080i/60 720p/60 ramb36 h.264 integer transform fpga 7831 8627 h.264 microsoft 1080p field pattern virtex 4 vs spartan 3e vhdl code motion 1080i vs 1080p	PDF
RAMB16 Abstract: 3s500e-5 RFC1321 Contextual Info:  Compliant to the RFC1321 Com- pliant to the RFC1321 specification of MD5. MD5 MD5 Hash Function Core The MD5 core is a high performance implementation of the MD5 Message Digest algorithm, a one-way hash function, compliant with RFC1321. The core is composed of two	Original	rfc1321 512-bit 75mbps ramb16 +13s500e-5	PDF
RAMB16 Abstract: RAMB18X2SDP verilog for 8 point dct in xilinx what the difference between the spartan and virtex RAMB18X2 huffman decoder verilog RAMB18X2s Contextual Info:  Conforms to the spatial LJPEG-D Lossless JPEG Decoder Core sequential lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T.81 recommendation).  Standalone operation. o ISO/IEC 10918-1 JPEG stream input. o Decoded pixel samples out-	Original	ramb16 ramb18x2sdp verilog for 8 point dct in xilinx what the difference between the spartan and virtex +3ramb18x2 huffman decoder verilog ramb18x2s	PDF
RAMB36 Abstract: AC127 MULT18X18 YUV400 AC-91 AC123 Contextual Info: H.264 CABAC Encoder Core v1.0 DS603 v1.0 May 31, 2007 Advance Product Specification Features LogiCORE Facts • H.264/MPEG-4 Part 10 Main/High/High Ext. Profiles Level 4.2+ Core Specifics Virtex™-5, Virtex-4, Spartan™-3E Supported Device Families	Original	ds603 264/mpeg-4 1080i 1080i/p +7ramb18x2 ramb36 ac127 mult18x18 yuv400 ac-91 ac123	PDF
RAMB36 Abstract: addressing mode in core i7 Macroblock 720P vhdl code for adaptive filter jm102 Contextual Info: H.264 Deblocker Core v1.0 DS592 v1.0 May 31, 2007 Product Specification Introduction LogiCORE Facts The H.264 Deblocker Core Version 1.0 is a fully functional VHDL design implemented on a Xilinx FPGA and delivered in netlist form. The Deblocker core accepts input parameters and macroblocks to deblock	Original	ds592 264/avc/mpeg4 do-di-h264-deblock ramb36 +5addressing mode in core i7 macroblock 720p vhdl code for adaptive filter jm102	PDF