1240 G 1G Search Results

phl99

Abstract: LAL 2.25 SN74ALS1240 ALS240 SN54ALS1240
Contextual Info: TYPES S N 5 4 A L S 1 2 4 0 , S N 5 4 A L S 1 2 4 1 , S N 7 4 A L S 1 2 4 0 , S N 7 4 A L S 1 2 4 1 OCTAL BUFFERS A ND LINE DRIVERS W IT H 3-S TA TE O UTPUTS D 2 6 6 1 , DECEM BER 1 9 8 2 -R E V IS E D DECEM B ER 1 9 8 3 S N 54A LS 1240, SN 54A LS 1241 . J P AC KA G E

Contextual Info: *SYNERGY PR O G R A M M A B LE DELAY CHIP SEMICONDUCTOR FEATURES Clockworks SY10E195 SY100E195 DESCRIPTION Up to 2ns delay range =£Ops/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195

Contextual Info: * PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195 PIN CONFIGURATION N CO T

Contextual Info: SN54ALS1240, SN74ALS1240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS D 2 6 6 1 , D E C E M B E R 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 SN 54A LS 1240 . . . J PACKAGE S N 74A LS1240 . . . DW OR N PACKAGE Low-Power Version of 'A L S 2 4 0 A • 3-S tate Outputs Drive Bus Lines or Buffer

Contextual Info: * Clockworks SY10E195 SY100E195 PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range Extended 100E V ee range of -4.2V to -5.5V ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry 75Kk£2 input pulldown resistor

Contextual Info: * Clockworks SY10E195 SY100E195 PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range Extended 100E V ee range of -4.2V to -5.5V ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry 75KkH input pulldown resistor

Contextual Info: * Clockworks SY10E195 SY100E195 PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range Extended 100E V ee range of -4.2V to -5.5V ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry 75KkH input pulldown resistor

AL sn11

Abstract: 240-PIN 64MX8 850C PC2-5300 samsung pc2-5300
Contextual Info: Product Specifications PART NO: REV: 1.2 VL395T2953-E6/D5 General Information 1GB 128Mx72 DDR2 SDRAM FULLY BUFFERED ECC 240 PIN DIMM FBDIMM Description: The VL395T2953 is a 128M X 72 DDR2 SDRAM high density Fully Buffered DIMM(FBDIMM). This memory module consists of eighteen CMOS 64MX8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages,

Contextual Info: Product Specifications PART NO: REV: 1.2 VL395T2953-E6/D5 General Information 1GB 128Mx72 DDR2 SDRAM FULLY BUFFERED ECC 240 PIN DIMM FBDIMM Description: The VL395T2953 is a 128M X 72 DDR2 SDRAM high density Fully Buffered DIMM(FBDIMM). This memory module consists of eighteen CMOS 64MX8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages,

Contextual Info: * Clockworks SY10E196 SY100E196 PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES Up to 2ns delay range Extended 100E V ee range of -4 .2 V to -5 .5 V ~20ps digital step resolution Linear input for tighter resolution >1GHz bandwidth

Contextual Info: SAMSUNG ELECTRONICS INC b?E J> m 7 ^ 4 1 4 2 QGlS2ba 07S KMM5364100/G DRAM MODULES 4M X 36 DRAM SIMM Memory Module FEATURES GENERAL DESCRIPTION • Performance range: I rac tcAC I rc 60ns 15ns 110ns KMM5364100-7 70ns 20ns 130ns KMM5354100-8 80ns 20ns 150ns

Contextual Info: * Clockworks SY10E196 SY100E196 PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES Up to 2ns delay range Extended 100E V ee range of -4 .2 V to -5 .5 V ~20ps digital step resolution Linear input for tighter resolution >1GHz bandwidth

12J5

Abstract: 74ALS DM74ALS1240A DM74ALS1240AN DM74ALS1240AWM ALS240 DM74ALS240
Contextual Info: S E M IC O N D U C T O R tm DM74ALS1240A Octal 3-STATE Bus Driver Features • Advanced oxide-isolated, ion-im planted S c h o ttk y T T L process Connection Diagram Function Table ’ALS1240A 20 — Vcc 1G — 1 1A1 — 2 19 — 2G 2Y4 — 3 18 — 1Y1 U

DM 024

Abstract: DDR266 DDR333 PC2100 PC2700 WV3EG265M64EFSU-D4
Contextual Info: White Electronic Designs WV3EG265M64EFSU-D4 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION Double-data-rate architecture The WV3EG265M64EFSU is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen

Contextual Info: White Electronic Designs WV3EG265M64EFSU-D4 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION „ Double-data-rate architecture „ PC2700 and PC2100 „ Bi-directional data strobes DQS „ Differential clock inputs (CK & CK#) The WV3EG265M64EFSU is a 2x64Mx64 Double Data

K 176 LE, K 561 LN

Contextual Info: itic H ic o n ALUMINUM ELECTROLYTIC CAPACITORS PF Approved by Reliability Center for Electronic Component, Japan-Certification No. RCJ-03- 23C Low Im pedance, High Reliability • Low impedance and high reliability withstanding 5000 hour load life at +105°C 3000/2000 hours

1240a

Abstract: ic 1240A
Contextual Info: R C H I I - D S E M IC O N D U C T O R tm DM74ALS1240A Octal 3-STATE Bus Driver Features • A dvanced oxide-isolated, ion-im planted S chottky TT L process Connection Diagram Function Table 1 1A1 — 2 19 — 2G 2Y4 — 3 18 — 1Y1 ■ Low pow er dissipation version o f th e D M 74ALS240, 241

Contextual Info: The Leading Source for EMI Shielding Reliable Board, Enclosure and Cable Solutions flat cable clamp - flat cables up to 50-conductor widths B WITH DUAL PRESS FIT MOUNTS. Ferrite assembly bonded in nylon mounting clamp; easily installed by pressing the integral spring tab

CLEVO

Abstract: LP2600T SERVICE MANUAL lg r500 71P26 Insyde bios manual 71-P2205-001A 71-P2205-001 LCD PC LP2600T CA194 LP-2600
Contextual Info: PREFACE SERVICE MANUAL LCD PC LP2600C/LP2600T I SERVICE MANUAL NOTICE The company reserves the right to revise this publication or to change its contents without notice. Information contained herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume

l 101c 681

Abstract: pj 986 iv PJ 986 pj 979 code
Contextual Info: m e ki con. ALUMINUM ELECTROLYTIC CAPACITORS PF Low Im pedance, High R eliability Approved by Reliability Center for Electronic Component, Japan-Certification No. RCJ-03-23C series • Low impedance and high reliability withstanding 5000 hour load life at + 1 0 5 t: 3000/2000 hours

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2ns Worst Case Delay Range =20ps / Delay Step Resolution >1 GHz Bandwidth On Chip Cascade Circuitry Extended 100E VEE Range of -4.2V to -5.46V i ; The MC1OE/1OOE195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment.

12 bit ADC

Contextual Info: y n y jx iy n _ A/D C onverters A/D Converters, Product Tables and Trees. 7-2 MAX 104 MAX115 MAX116 MAX125 MAX126 MAX146 MAX 147

Contextual Info: w Y 3? W >R DESCRIPTION • Up to 2ns delay range ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ =20ps/digitai step resolution ■ >1 GHz bandwidth ■ On-chip cascade circuitry ■ 75Kki2 input pulldown resistor ■ Fully com patible with M otorola MC10E/100E195

Contextual Info: * Clockworks SY10E196 SY100E196 PR O G R A M M A B L E DELAY CHIP WITH AN AL OG INPUT SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • Up to 2ns delay range ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ - 20ps digital step resolution ■ Linear input for tighter resolution