100LE Search Results

180LETa

Abstract: 160LET 32let 450LMT 50LET 63LET 100LET 80LET 35LET
Contextual Info: BIF Document Semiconductor Fuse 25-180A, 240 Volts 35785293 Size 104 6 4 2 103 6 4 2 102 80LET 100LET 125LET 160LET 180LETa 6 4 Virtual Pre-Arcing Time In Seconds 2 101 6 4 25LET 32LET 35LET 50LET 63LET 2 100 6 4 2 10–1 6 4 2 10–2 6 4 2 10–3 6 4 2 10–4

Contextual Info: SSRAM AS5SS256K36 256K x 36 SSRAM PIN ASSIGNMENT Top View Flow-Through, Synchronous Burst SRAM 100-pin TQFP (DQ, DQC & DQCR) FEATURES              DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss

AT91SAM3U4

Abstract: at91sam3 1N1308 MAR 735 REGULATOR IC 7912 pin identify AT91SAM3U4E SAM3u1 AT91SAM3U 3961 G.E 0x20180
Contextual Info: Features • Core • • • • • • – ARM Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit MPU – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

atxmega128B

Abstract: 141-003 0x0D00 XMEGA Application Notes
Contextual Info: 8/16-bit Atmel XMEGA B1 Microcontroller ATxmega128B1; ATxmega64B1 Features  High-performance, low-power Atmel AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories          64K - 128KBytes of in-system self-programmable flash

ATMEGA 326

Abstract: ATMEGA325A-AUR ATMEGA645A-AU ATMEl 326
Contextual Info: Features • • • • • • • • • • • High Performance, Low Power Atmel AVR® 8-Bit Microcontroller Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers

ADSP-21489 user manual

Abstract: ADSP-21487 sharc ADSP-214xx FFT Accelerator medialb ADSP-21160 ADSP-21161 ADSP-21489 ADSP21487 sharc iir filter IBIS Model diode
Contextual Info: SHARC Processor SUMMARY The ADSP-2148x processors are available with unique audiocentric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

ultra fast pulse generator

Abstract: 32P4938A
Contextual Info: SSI 32P4938A PR4ML Read Channel with 16/17 ENDEC w/Thermal Asperity Suppression March 1998 • 4 bit nibble and byte wide bi-directional NRZ data interfaces The part is a high performance BiCMOS read channel IC that provides all of the functions needed to

GS8161Z18AT-300

Abstract: gs816
Contextual Info: Preliminary GS8161Z18/36AT-300/275/250/225/200 18Mb Pipelined and Flow Through Synchronous NBT SRAM Flow Through 2-1-1-1 1.8 V 2.5 V 300 345 300 340 275 320 275 315 250 295 250 285 230 265 225 260 mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5

64KX32

Abstract: 7C1334-100 7C1334-133 7C1334-50 7C1334-80 CY7C1334
Contextual Info: fax id: 1084 CY7C1334 PRELIMINARY 64Kx32 Pipelined SRAM with NoBL Architecture Features • Low 16.5 mW standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ device MT55L64L32P • Supports 133-MHz bus operations with zero wait states

disc drive servo demodulator

Abstract: transistor servo drive 32P4918B
Contextual Info: SSI 32P4918B PR4ML Read Channel with 8/9 ENDEC and Area Detect Servo March 1998 Functional blocks include a bi-directional serial port, an automatic gain control amplifier, a programmable filter, an offset canceller, a peak detecting pulse qualifier, an adaptive transversal filter, a Viterbi qualifier

Contextual Info: Preliminary GS816019/33/37AT-300/275/250/225/200 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features 300 MHz–200 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Byte Write and Global Write • 1.8 V or 2.5 V +10%/–10% core power supply

USR24

Abstract: ssi protocol 73D2248
Contextual Info: SSI 73D2248/2348 & MNP5, V.42bis Datacom Modem Device Set i k m M s l m s ' A TDK Group/Company Advance Information January 1993 FEATURES DESCRIPTION The SSI 73D2248/2348 Chip Sets consists of two CMOS integrated circuits which provide the data pump and protocol functions required to implement a high

m systems pcmcia

Contextual Info: SSI 78Q8378 óécmsvskms Enhanced PCMCIA Ethernet Device A TDK Group/Company Target Specification December 1994 DESCRIPTION FEATURES The SSI 78Q8378 is a highly integrated Ethernet 1C for use in PCMCIA Personal Computer Memory Card International Association applications with MultiFunction card capability, especially Ethernet/Modem

64KX32

Abstract: 7C13 CY7C1329
Contextual Info: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

80486 microprocessor block diagram and pin diagram

Abstract: 64KX32 CY7C1336
Contextual Info: 36 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
Contextual Info: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

7C13

Abstract: CY7C1335
Contextual Info: fax id: 1045 1CY 7C13 35 PRELIMINARY CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 660 µW standby power (f=0, L version) The CY7C1335 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

MN66261

Abstract: tc9263f
Contextual Info: ABRIDGED VERSION SSI 33C3910 ¿éconsuskms ATAPI CD-ROM Disk Decoder A TDK G roup/Company A d v a n c e Information December 1995 DESCRIPTION FEATURES The SSI 33C3910 ATAPI CDROM Disk Decoder is a CMOS monolithic integrated circuit housed in a 100pin QFP package. Operating at five volts, the controller

Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 100 MHz Data Rate for Video and other High-Speed Applications ❑ One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

32p4904-cg

Abstract: 32P4904 PR48
Contextual Info: ABRIDGED VERSION c m m M SSI 32P4904 PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo tm A TDK Group/Company February 1996 DESCRIPTION Serial Interface port for access to Internal program storage registers The SSI 32P4904 is a high performance BiCMOS read

RC3T

Abstract: j3248 32H4631 320930
Contextual Info: S I LI CO N S Y S T E M S INC blE T> m ô 2 5 3 T b S 0 D D 7 2 3 H 111 • SIL SSI 32C9001 PC-AT Combo Controller With Reed Solomon, 48 Mbit/s flô lL s l i m s u s k m s A TDK Group#Company 3 ro u p /c Advance Information January 1993 DESCRIPTION FEATURES

32c9001

Contextual Info: SSI 32C9001 PC-AT Combo Controller With Reed Solomon, 48 Mbit/s ¿ é c m s u s k m s A TDK G roup/C om pany Advance Information January 1994 DESCRIPTION FEATURES The SSI 32C9001 is an advanced CMOS VLSI device which integrates major portions of the hardware