10032 Search Results

100325PC

Abstract: F100K M24B MO-047 MS-013 N24E V28A 100325QC 100325QI 100325SC
Contextual Info: Revised August 2000 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential

100323PC

Abstract: 100323QC F100K MO-047 N24E V28A
Contextual Info: Revised August 2000 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own

F100K

Abstract: J24E W24B
Contextual Info: October 19, 2009 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own respective ground connection. Transition times were designed to be

Contextual Info: Revised November 1999 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own

DS009879

Contextual Info: Revised November 1999 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential

F100K

Contextual Info: 100321 Low Power 9-Bit Inverter General Description The 100321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. All inputs have 50 kΩ pull-down resistors. n n n n n 2000V ESD protection Pin/function compatible with 100121

Contextual Info: S E M IC O N D U C T O R tm 100322 Low Power 9-Bit Buffer General Description • 2000V ESD protection The 100322 is a m onolithic 9-bit buffer. The device contains nine non-inverting buffer gates w ith single input and output. All inputs have 50 kQ pull-down resistors and all outputs are

Contextual Info: S E M IC O N D U C T O R tm 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex tra n sla tor fo r converting F100K logic levels to T T L logic levels. D ifferential inputs allo w each circuit to be used as an inverting, non-inverting or differential re­

100329PC

Abstract: 100329QC 100329QI MO-047 N24E V28A
Contextual Info: Revised August 2000 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined by the DIR input. A LOW on the output enable input

Contextual Info: Nationa I Semiconductor M ILITARY DATA SHEET 100322-X REV OBO 0r g ^Lt nSte bS; oeSS Last Major Revision Date: 10/30/95 LOW POWER 9-BIT BUFFER General Description The 100322 is a monolithic 9-bit inverter. The device contains nine non-inverting buffer gates with single input and output.

b37 diode

Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides

VOM55

Abstract: swadj
Contextual Info: Power Management ICs for Mobile Phones High Efficiency Power Management IC No.10032EAY03 BH6176GU ●Description The application circuit is recommended for use. Make sure to confirm the adequacy of the characteristics. When using the circuit with changes to the external circuit constants, make sure to leave an adequate margin for external

Contextual Info: MGL S -10032D 100 X 32 DOTS 0.38 0.43 0.05 0.05 1 2 vss VDD 3 VO 4 À0 5 R/ff 6 El 7 E2 8 NC 9 DBO 10 DB1 11 12 13 DB2 DB3 DB4 14 DB5 15 DB6 16 DB7 * 17 LED+ 18 LED- OR EQUIVALENT

ns108

Abstract: F100K
Contextual Info: S E M IC O N D U C T O R tm 100321 Low Power 9-Bit Inverter General Description The 100321 is a m onolithic 9-bit inverter. The device con tains nine inverting buffer gates with single input and output All inputs have 50 kQ pull-dow n resistors. • 2000V ESD protection

F100K

Abstract: 100324
Contextual Info: 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable E , when LOW, holds all inverting outputs HIGH and holds all

U1407

Contextual Info: POWERTIP PO 10032-A OUTLINE DIMENSION 4 BLOCK OIAGRAM 3 .0 . PAD R2 0 85 2 * 0 .5 782 - H O — -P2.54 x 19=48 26 not o1n -HV- PAO * 4 0 1 -H 2 - *• 2.0 4 #10 A 6 < K 7 1 W o s 1 2-R1 25 PAD 2*R2 0 42 $ ICO PANEI SEO 1520 SEO 1521 S E 0 1520

100323PC

Abstract: 100323QC F100K MO-047 MS-011 N24E V28A
Contextual Info: n U 'y19!8 M K icoo R e v is e d N o v e m b e r 199 9 TM 100323 Low Power Hex Bus Driver General Description Features T h e 1 0 0 3 2 3 is a m o n o lith ic d e v ic e c o n ta in in g s ix b u s d riv ­ • 5 0 % p o w e r re d u c tio n o f th e 1 0 0 1 2 3

Contextual Info: A ugust 1998 100322 Low Power 9-Bit Buffer General Description • 2000V ESD protection The 100322 is a m onolithic 9-bit buffer. The device contains nine non-inverting buffer gates w ith single input and output. All inputs have 50 kQ pull-down resistors and all outputs are

Contextual Info: 100324 £3 National ÆÆ Semiconductor 100324 Low Power Hex TTL-to-ECL Translator General Description The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are com­ patible with standard or Schottky TTL. A common Enable

100125

Abstract: F100K J24E
Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential receiver. An internal reference voltage generator provides VBB

F100K

Contextual Info: 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined

F100K

Abstract: J24E W24B
Contextual Info: 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable E , when LOW, holds all inverting outputs HIGH and holds all

diodes B2V datasheet

Abstract: C1995 F100K J24E N24E V28A W24B CP2121
Contextual Info: 100329 Low Power Octal ECL TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa The direction of the translation is determined by the DIR input A LOW on the output enable input

5962-9153001MYA

Abstract: 100324J-QMLV ECL 100124 100324DMQB 5962-9153001MXA
Contextual Info: National P/N 100324 - Low Power Hex TTL-to-ECL Translator Products > Military/Aerospace > Logic > ECL > 100324 100324 Product Folder Low Power Hex TTL-to-ECL Translator General Description Features Package & Models Datasheet Samples & Pricing Datasheet Title