0X000 Search Results

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

MC68HC05

Abstract: MC68HC11 MPC823 MC68302 MC68328 MC68360
Contextual Info: Communication Processor Module The expected results are as follows: SMC • The TX buffer descriptor Ep0 CONTROL/STATUS field must contain 0x3800. • The TX buffer descriptor (Ep0) DATA LENGTH field must contain 0x0003. • The TX buffer descriptor (Ep1) CONTROL/STATUS field must contain 0x3c80.

0x00000010

Abstract: 0x300000C0 0x0000000b E 32.0000 C 000D 10B5 0x300000C4 0x10000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060/68040 DEMO Memory Map 06/24/96 PCI Configuration Registers PCI CFG Offset BIT 0x00000000 0-15 0x00000002 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

0x00000564

Abstract: 0x00000404 0x00000532 0x0000047C 0x000005BE STI3400 0x0000040A sgs 8 r 15 93CS46 0x0000045C
Contextual Info: PLX Technology SGS PCI MPEG Board I/O MAP 07/15/96 PCI Configuration Registers PCI CFG Offset 0x00000000 0x00000002 BIT 0-15 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

80C517

Abstract: DS80C320 EMUL51-PC OMF51
Contextual Info: CHIPTOOLS, INC. ChipView -51 Chip Vie w®-51 High-Level/Low-level Debugger *»• MlUIO •ifhhta ,’l t i t r«4 <0x«K0«m ,7 f IM S 'ièxw m yi 0X0006u (0 x0 00 0 >> J i t hi® CftM tNM tem ,’l t i b i U »ML. ▲ No learning curve— ChipView-51 is keycom patible with B orlands’s popular turbo

Contextual Info: CY7C63411/12/13 TfffFnnmrm.v CY7C63511/12/13 ,/C IP R E S S 6.0 Memory Organization 6.1 Program Memory Organization after reset 14-bit PC Address -^ 0x0000 Program execution begins here after a reset. 0x0002 USB Bus Reset interrupt vector 0x0004 128 is timer interrupt vector

Contextual Info: RGB640 10.0 Register Descriptions 10.1 0x0000 Identification 7 6 5 4 3 2 1 IDLO POR: 0x1 C Bits 7 0: ID LO - The low byte of the product identification code. 0x1 C 10.2 0x0001 Identification / Revision Level 7 6 5 4 3 REV 4: Bits 3 0: 48 1 IDHI 0x12 POR:

Contextual Info: RGB528A 8.0 Power Management The following registers are used to control power dissipation: □ Power Managem ent index 0x0005 □ Miscellaneous Clock Control (index 0x0002) □ Sync Control (index 0x0003) □ Miscellaneous Control 1 (index 0x0070) 8.3 Clocking Power

Contextual Info: ¿¿PD30111 NEC 6. DMAAU DMA ADDRESS UNIT DMAAU controls the addresses for the DMA operations between A lU /lrD A 4-M bps communication module (FIR) and memory. The DMA start address of each DMA channel can be specified in a range of 0x0000 0000 through 0x01 FF FFFE

0X000F

Abstract: C800 MPC555 c880 0000FFFF MPC566
Contextual Info: Motorola MPC5xx Memory Maps Address* 0x0000 0x0003 0x0004 0x0006 0x0007 0x0007 0x0008 0x000F 0x0010 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x002F 0x0030 0x0030 0x0030 0x0030 0x0030 0x0030

0X13

Abstract: 0x40 0b10000000 0B11000000
Contextual Info: The application code of PWM function. IOC9 = 0X9 IOCA = 0XA R10 = 0X10 ;PWM COUNTER R11 = 0X11 ;PWM COUNTER R12 = 0X12 ;TEMP R13 = 0X13 ;TEMP R14 = 0X14 ;TEMP ERE = 0XE ORG 0X000 INITIAL: MOV A,@0B11001000 ;SELECT EXTRA RAM IOW IOCA CLRA IOW IOC9 CLR R10

0B11000000

Abstract: 0X13 0b10000000
Contextual Info: 義隆電子股份有限公司 ELAN MICROELECTRONICS CORP. The application code of PWM function. IOC6 = 0X6 IOC8S = 0X8 R8S = 0X08 ;PWM COUNTER R9S = 0X09 ;PWM COUNTER R12 = 0X12 ;TEMP R13 = 0X13 ;TEMP R14 = 0X14 ;TEMP ERE = 0XE ORG 0X000 INITIAL:

Contextual Info: PRELIMINARY TECHNICAL DATA AD6623 DATA SHEET a Four Channel, 104 MSPS Digital Transmit Signal Processor TSP Preliminary Technical Data AD6623 AD6622 mode by selecting bit 7 of address 0x000 low. An external Digital-to-Analog Converter (DAC) is all that is

MCF54452

Abstract: M5445EVB JP912 MCF54450 MCF54454 MCF54455 hyperterminal 0x80000000-0x8FFFFFFF i phone 4 pin map MCF54453
Contextual Info: ColdFire MCF5445x Internal Peripheral Space Memory Map MCF5445x Family Configurations Base Address Slot # Internal Address[31:28] Address Range Destination Slave Slave Memory Size 0xFC00_0000 SCM MPR and PACRs 00xx 0x0000_0000–0x3FFF_FFFF FlexBus 1024 MB

MCF54452

Abstract: MCF54450 MCF54454 MCF54455 m54455 M54451EVB
Contextual Info: ColdFire MCF5445x Internal Peripheral Space Memory Map Peripheral System Memory Map MCF5445x Family Configurations Base Address Slot # Internal Address[31:28] Address Range Destination Slave Slave Memory Size 0xFC00_0000 SCM MPR and PACRs 00xx 0x0000_0000–0x3FFF_FFFF

B-528

Contextual Info: RGB528A C.O -A Revision Level 4. The original RGB528 is replaced with the "-A" revision RGB528A . The new revision has the following changes from the original: 1. The RG B528A has a bit in the Miscellaneous Clock Control register (index 0x0002) called S C L K INVT.

1N4148/2 pin connector sip

Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Contextual Info: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000

512* display

Abstract: bt.656 to RGB lcd 240 128 S5D2400X bt.656 to RGB display 120 video scaler lcd monitor
Contextual Info: S5D2400X Data Sheet Revision 1.0 RECORD OF REVISIONS Rev. No Date 0.0 2003/10 1.0 2004/09 Page Description of Change First Release 39 42,43 5.12 Display Region Masking Control block addition Register Map addition 0x0007~0x0009, 0x000E~0x000F Table of Contents

Contextual Info: RGB526/RGB526DB 9.0 Power Management T h e follow ing re g iste rs a re u se d to control pow er d issi­ p atio n : 9.1 □ P ow er M a n a g e m e n t index 0x0005 □ M iscellaneous Clock C ontrol (index 0x0002) □ Sync C ontrol (index 0x0003) □ M iscellaneous C ontrol 1 (index 0x0070)

0xD0000000-0xDFFFFFFF

Abstract: 0x80000000-0xBFFFFFFF 80960CA 82596CA 0x20000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060 DEMO Memory Map 06/16/96 80960CA Address Space 0x00000000-0x0000003F 0x00000040-0x000000BF 0x000000C0-0x000000FF 0x00000100-0x000003FF 0x00000400-0X0FFFFFFF 0x10000000-0x1FFFFFFF 0x20000000-0x2FFFFFFF 0x30000000-0x3FFFFFFF 0x40000000-0x7FFFFFFF

16V8H-15

Abstract: U0401 20-2136J PT3877 16v8h 1n4148 0805 20V8H IC 4020 512 eeprom dip 32-pin HEADER 10X2
Contextual Info: PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) 0x00000002 0-15 Device ID, Allocated by PLX (Read-only) (Default = 9060)

tyal 206

Abstract: TYAL
Contextual Info: TOSHIBA TMPR3907F TENTATIVE TOSHIBA RISC PROCESSOR TMPR3907F 32-Bit TX System RISC 1. GENERAL DESCRIPTION The TMPR3907F TX3907 is a TX39 family microprocessor incorporating a 32-bit TX39/H core developed by Toshiba. Designed for use in OA equipment, the TX3907 also incorporates such peripheral circuits as a memory controller, a PCI

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

mip 291

Abstract: mip 290
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)