ZEROPOWER Search Results

02APR

Contextual Info: M48Z35 M48Z35Y 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages:

Contextual Info: M4Z28-BR00SH M4Z32-BR00SH ZEROPOWER SNAPHAT® battery Datasheet - production data Description The M4Zxx-BR00SH SNAPHAT® top is a detachable lithium power source for ST’s nonvolatile ZEROPOWER® surface-mount SOIC package 28-pin . The SNAPHAT top contains a lithium battery and

DS1220

Abstract: M48Z02 M48Z12 24-Pin Plastic DIP
Contextual Info: M48Z02 M48Z12 5 V, 16 Kbit 2 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection

DS1225

Abstract: M48Z08 M48Z18 M4Z28-BR00SH M4Z32-BR00SH SOH28 ram DS1225
Contextual Info: M48Z08 M48Z08Y, M48Z18 5V, 64 Kbit 8Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM and POWER-FAIL CONTROL CIRCUIT ■ UNLIMITED WRITE CYCLES ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT

M40Z300

Abstract: M48Z128 M48Z128V M48Z128Y SOH28
Contextual Info: M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, AND BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

Contextual Info: M48Z35AY M48Z35AV 256 Kbit 32Kb x8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY S N A P H A T (SH) Battery ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ BATTERY LOW FLAG (BOK) ■ AUTOMATIC POWER-FAIL CHIP DESELECT

Contextual Info: M48Z512 M48Z512Y SGS-THOMSON IIIIM J ì ILIì M W IIÈ Ì 4 Mb 512K x 8 ZEROPOWER SRAM NOT FOR NEW DESIGN INTEGRATED LOW POWER SRAMs, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 5 YEARS of DATA RETENTION in the

MK48Z30

Contextual Info: S5E D • 7 ^ 2 3 7 003fl3flb T13 ■ SGS-THOMSON SGTH T - ^ - 2 L 3 “ / J MK48Z3Ö MK48Z30Y S G S- THOMSON CMOS 32K x 8 ZEROPOWER SRAM ■ INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT AND BAT­ TERY. ■ UNLIMITED WRITE-CYCLES. ■ READ-CYCLE TIME EQUALS WRITE-CYCLE

Contextual Info: ¿77SGS-THOMSON M 48Z35 A T # . [M O g M |[L I« (M [](g f_ M 4 8 Z 3 5 Y 256Kb (32K x 8) ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and

Contextual Info: /T T SGS-THOMSON ^ 7#. llD M ILi sraMD(@l> M48Z58 CMOS 8K x 8 ZEROPOWER SRAM PRODUCT CONCEPT INTEGRATED LOW POWER SRAM and POWER-FAIL CONTROL CIRCUIT PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 8K x 8 SRAMs SELF CONTAINED BATTERY in the CAPHAT DIP PACKAGE

MK48T18B15

Abstract: MK48T18B10 MK48T18B-20 MK48T08B-15 MK48T18B20 MK48T18b-15 MK48T08B15 MK48T08B10 MK48T08B20 MK48T18B
Contextual Info: • r z ^ 7 # 7 ^ 537 0 0 5 7^5 7 R ■ j S C S -T H O M . H in ig E O ilL iM W n E S < ' ¿ ib 'Z Z - ^_ S O N S G S-THOMSON M K 4 8 T 0 8 /1 8 (B _ - 1 0 / 1 5 / 2 0 3QE D T IM E K E E PE R 8 K X 8 ZEROPOWER™ RAM ■ INTEGRATED ULTRA LOW POWER SRAM,

Contextual Info: SCS-THOMSON MKI48Z18 CMOS 8K x 8 ZEROPOWER SRAM ADVANCE DATA • INDUSTRIAL TEMPERATURE RANGE -40‘C TO +85"C ■ INTEGRATED LOW POWER SRAM, POWERFAIL C O N TR O L C IR C U IT AND ENERGY SOURCE ■ UNLIMITED WRITE-CYCLES. ■ READ-CYCLE TIME EQUALS WRITE-CYCLE

Contextual Info: 55E /T T *7 # . P • 7 ^ 5 3 7 0036365 S C S -1 H O M S O N * [l» [i g « M (g § 376 s 6 ■S6TH T -H é -¿ 3 - / s - thomson M K I4 8 Z 1 8 CMOS 8K x 8 ZEROPOWER SRAM ADVANCE DATA ■ INDUSTRIAL TEMPERATURE RANGE -40‘C TO +85"C ■ INTEGRATED LOW POWER SRAM, POWERFAIL CO NTRO L C IR C U IT AND ENERGY

Contextual Info: /T T SGS-THOMSON M48Z02 A 7 # . [M»[g[LI gmMD(gS_ M48Z12 16Kb (2K x 8 ZEROPOWER SRAM • INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ UNLIMITED WRITE CYCLES ■ READ CYCLE TIME EQUALS WRITE CYCLE TIME ■ AUTOMATIC POWER-FAIL CHIP DESELECT and

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0V OR 3.3V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

M48Z512

Contextual Info: M48Z512 M48Z512Y CMOS 512K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAMs, POWER-FAIL CONTROL CIRCUIT and BATTERIES CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 5 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 512K x 8 SRAMs

M48Z35

Abstract: M48Z35Y SOH28 caphat
Contextual Info: M48Z35 M48Z35Y 256Kb 32K x 8 ZEROPOWER SRAM INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage):

DS1225 circuit diagram

Abstract: DS1225 M48Z08 M48Z18 SOH28 DS1225 date code
Contextual Info: M48Z08 M48Z18 64Kb 8K x 8 ZEROPOWER SRAM INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES

M48Z129V

Abstract: M48Z129Y
Contextual Info: M48Z129Y M48Z129V 5.0 V or 3.3 V, 1 Mbit 128 Kb x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of

M48Z59

Abstract: M48Z59Y SOH28
Contextual Info: M48Z59 M48Z59Y 64Kb 8K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION

M48Z512A

Abstract: M48Z512AY
Contextual Info: M48Z512A M48Z512AY 4 Mb 512K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT

PCDIP24

Abstract: M48Z02 Zeropower DS1220 M48Z02 M48Z12
Contextual Info: M48Z02 M48Z12 16Kb 2K x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES

M48Z30

Abstract: M48Z30Y
Contextual Info: M48Z30 M48Z30Y CMOS 32K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x 8 SRAMs

DS1225

Abstract: DS1225 circuit diagram M48Z08 M48Z18 SOH28 MH181
Contextual Info: M48Z08 M48Z18 64 Kbit 8Kb x 8 ZEROPOWER SRAM DATA BRIEFING INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES