LDIP32 Search Results

Contextual Info: M48Z512 M48Z512Y SGS-THOMSON IIIIM J ì ILIì M W IIÈ Ì 4 Mb 512K x 8 ZEROPOWER SRAM NOT FOR NEW DESIGN INTEGRATED LOW POWER SRAMs, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 5 YEARS of DATA RETENTION in the

si977

Abstract: 48Z512Y
Contextual Info: /=7 SGS-TtfOMSON ^ 7 # M 48Z512 M 48Z512Y M ^ © iL [i g ? ^ (Q iO (g S CMOS 512K X 8 ZEROPOWER SRAM PRELIMINARY DATA • INTEGRATED LOW POWER SRAM, POWERFAIL CO N TRO L CIRCUIT AND BATTERY ■ C O N V E N T IO N A L SRAM O P E R A T IO N ; UN­ LIMITED W RITE CYC LES

M48Z512

Contextual Info: M 48Z512 M 48Z512Y w , S G S -T H O M S O N k7 #» RitlDÊlMIlilLIKËinSMQtÊS 4 Mb 512K x 8 ZER O PO W ER SRAM N O T F O R N E W D E S IG N INTEGRATED LOW POWER SRAMs, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES

Contextual Info: M48Z512 M48Z512Y SGS-THOMSON 4 Mb 512K x 8 ZEROPOWER SRAM NOT FOR NEW DESIGN INTEGRATED LOW POWER SRAMs, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 5 YEARS of DATA RETENTION in the ABSENCE of POWER AUTOMATIC POWER-FAIL CHIP DESELECT