YD 1048 Search Results

Casio 1026

Abstract: AD512 HSPPAR
Contextual Info: BOARD PRODUCTS TBP9L03 Display Controller Board 1. G E N ER AL DESCRIPTION T h e T B P 9 L 0 3 i s a n a d d i t i o n a l b o a r d f o r p e r s o n a l c o m p u t e r f o r r e a l i z i n g r e a l t i m e d i s p l a y o f 3d i m e n t i o n a l g r a p h i c s w ith T C 8 5 1 2 G I I S P lo a d e d for p e r f o r m i n g s h a d i n g p r o c e s s e s o f d i s p l a y

LC371000SP

Abstract: lc371000 CCA1 A2 SM20L
Contextual Info: Ordering number: EN3K5086A CMOS LSI LC371000SP, SM-10/LC371000SP, SM-20LV S A \Y O 1 MEG 131072 words x 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC371000SP, SM-10 and LC371000SP, SM-20LV are 1048576-bit M ask Program m able Read Only

Contextual Info: TO SH IBA TC55V1001 AF/AFT/ATR/AST/ASR-85,-10,-85L.-1 OL T O SH IB A M O S DIGITAL INTEGRATED CIRCUIT SILICON GATE C M O S 131,072-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55V1001AF/AFT/ATR/AST/ASR is a 1,048,576-bit static random access memory SRAM organized as

M5M418165

Abstract: M5M4181 M5M418165BJ IS3015 M5M418165B m5m418
Contextual Info: Preliminary Spec. MITSUBISHI LSIs <*».*« M5M418165BJ,TP-6,-7,-8,-6S,-7S,-8S HYPER PAGE MODE 16777216-BIT 1048576-WQRD BY 16-BIT DYNAMIC RAM PIN C O N F IG U R A T IO N (T O P V IE W ) D E S C R IP T IO N This is a (amiiy of 1048576-word by 16-bit dynamic

HM511001-12

Abstract: HM511001
Contextual Info: H M 511001 S e r ie s 1048576-word x 1-bit CMOS Dynamic Random Access Memory The Hitachi HM511001 Series is a CMOS dynamic RAM organized 1,048,576-word x 1-bit. HM511001 has realized higher density, higher performance and various functions by employing 1.3jum CMOS process technology and some new CMOS circuit

Contextual Info: FU JITSU ECL 16384-BIT BIPOLAR RANDOM ACCESS MEMORY MBM10484-15 F e b ru a ry 1 9 8 8 E d itio n 2 .0 16384-BIT BIPOLAR ECL RANDOM ACCESS MEMORY The Fujitsu MBM 10484 is fully decoded 16384-bit ECL read/write random access memory designed for high-speed scratch pad, control and buffer storage

HM511000

Abstract: dynamic ram 8 bit hm511000 HM511000P M511000 HM511000-12 HM511000-10 HM511000JP-12 DG 402 rp HM511000ZP-12 ir 2210 ic
Contextual Info: HM511000 Series 1048576-word x 1-bit CMOS Dynamic Random Access Memory The Hitachi HM511000 Series is a CMOS dynamic RAM organized 1,048,576-word x 1-bit. HM511000 has realized higher density, higher performance and various functions by employing 1.3/im CMOS process technology and some new CMOS circuit

yd 1048

Abstract: E14YR AFPX-E16 AFPX-E14YR
Contextual Info: 可编程控制器 E16X 输入专用单元 E14YR 输出专用单元 扩展输入 专用单元 FP-X E16X 扩展输出 专用单元 FP-X E14YR 即使输出与输入不平衡 也能构成灵活的系统，节省多余消耗。 实现成本的削减以及安装空间的节约。

Contextual Info: 6 7 THIS DRAWING IS UNPUBLISHED. COPYRIGHT - 5 4 2 3 RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. LOC ALL RIGHTS RESERVED. DIST R E V IS IO N S 00 AD LTR DATE DESCRIPTION EC 0G3C 0 0 3 2 05 DWN APVD BSV DLS 26FEB 05 5.99 [.157] A -X- 1.27 1V 5

transistor f422 equivalent

Abstract: transistor f422 thomson CRT COLOUR TV SCHEMATIC DIAGRAM z80 ef9345 EF9345 TDA 9345 EF9367 TGS 813 difference between intel 8085 and motorola 6800 EF9345P
Contextual Info: GRAPHIC PROCESSORS DATABOOK 1st EDITION MARCH 1989 TABLE OF CONTENTS INTRODUCTION Page 4 GENERAL INDEX 5 PRODUCT GUIDE 7 ALPHANUMERICAL and SEMI-GRAPHIC CRT CONTROLLERS 11 GRAPHICS CONTROLLERS 105 COLOR PALETTE 213 APPLICATION NOTES 247 3 INTRODUCTION The SGS-THOMSON Graphics data book contains comprehensive data on three

TMS29F010

Contextual Info: TMS29F010 131072 BY 8-BIT FLASH MEMORY S M J S 8 4 0 - N O VEM BER 1997 • Single Power Supply 5 V ± 10% • • Organization . . . 131072 by 8 Bits Eight Equal Sectors of 16K Bytes - Any Combination of Sectors Can Be Erased - Any Combination of Sectors Can Be

m5m28f102j

Contextual Info: PRELIMINARY M5 M28F102P,FP,J,VP,RV-10,S-U12S-i 5S'S 1048576-BIT 65536-WORD B Y 16-BIT C M O S F L A S H M EM Q R V DESCRIPTION PIN CONFIGURATION (TOP VIEW The M itsubishi M 5 M 2 8 F 1 0 2 P ,F P J,V P JIV are high-speed

thomson CRT COLOUR TV SCHEMATIC DIAGRAM

Abstract: z80 ef9345 SS 1091 asn EF9367 transistor f422 equivalent marking codes transistors SSs processor 8035 practical circuits TDA 9345 EF9345FN EF7910
Contextual Info: GRAPHIC PROCESSORS DATABOOK 1st EDITION GRAPHIC PROCESSORS DATABOOK 1st EDITION MARCH 1989 TABLE OF CONTENTS INTRODUCTION Page 4 GENERAL INDEX 5 PRODUCT GUIDE 7 ALPHANUMERICAL and SEMI-GRAPHIC CRT CONTROLLERS 11 GRAPHICS CONTROLLERS 105 COLOR PALETTE 213 APPLICATION NOTES

N806

Abstract: Material density CDA 195 BL1-01 philips FW21 MHA301 Hall Effect 3 pin ugn 510H LQFP80 SAA9750H ugn2
Contextual Info: Philips Semiconductors Preliminary specification Camera Digital Signal Processor CAMDSP _ SAA9750H • Sync Signal Generator (SSG) to generate all necessary timing signals FEATURES • Y/C separator for mosaic filter colour CCD which can be

V02630

Abstract: 2051 16 pin DOT MATRIX 2088 2051 datasheet O101 SED1743 SED1748D0B 97um DOT MATRIX 8*8 2088 DOT MATRIX 2088
Contextual Info: SED1748 SED1748 LOW-POWER 160-BIT LCD SEGMENT DRIVER • DESCRIPTION The SED1748 is a 160-bit dot matrix LCD segment column driver for driving high-capacity LCD panels at duty cycles higher than 1/100 (up to 1/500). The LSI features a wide range of LCD drive voltages. The upper

l5442

Contextual Info: TMS29LF008T, TMS29LF008B 1048576-BYTE BY 8-BIT FLASH MEMORIES I * Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation • Organization: 1 024K Bytes x 8 Bits • Array Blocking Architecture - One 16K-Byte Protected-Boot Sector Two 8K-Byte Parameter-Sectors

fp1 PLC programming

Abstract: FP0-E32RS fp3 matsua Panasonic PLC FP communication marking code c14r fp3 matsushita AFPX-C30TD c14t EN61131-2 FP10SH
Contextual Info: • FP-X Control Unit Dimensions Unit: mm Dimensions when add-on cassettes (function and communication) are installed ●AFPX-C14 ∗ ∗ (The same dimensions apply to the expansion I/O unit AFPX-E16∗) COM Status display LED N X5 X3 X0 X2 X4 X7 X6 PROG. ERR.

ld25 cv

Contextual Info: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUSG17C - OCTOBER 1993 - REVISED SEPTEMBER 1998 I I I I I • • • • SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - M ilitary M -55°C to 125°C

idq10

Contextual Info: MITSUBISHI LSIs M6MGB/T162S4BVP 16,777,216-BIT 1,048,576 -WORD BY 16-BIT CMOS 3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (524,288-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) DESCRIPTION FEATURES The MITSUBISHI M6MGB/T162S4BVP is a Stacked Multi

FAUCET SENSOR CIRCUiT

Contextual Info: fe»*-.- i > ú it+* *«• lil' '•> *-3 * lv [llMlJWIjlIjlJIill A s m a ll e y e contributes for energy saving, comfort, convenience and safety O ur m o tio n s e n s o r is b ased on k n o w -h o w d ev e lo p e d o ve r m an y years, in c lu d in g o u r p ro p rie ta ry te c h n o lo g y fo r le n s e s , d e te c to r

Contextual Info: MITSUBISHI LSIs M6MGB/T08S2ATP 8388608-BIT 1 M x 8-BIT/512k x 16-BIT CMOS 3.3V-ONLY FLASH MEMORY & 2097152-BIT (256k x 8-BIT) CMOS STATIC RAM MCP (Multi Chip Package) FEATURES DESCRIPTION The MITSUBISHI M6MGB/T08S2ATP is a Multi Chip Package (MCP) that contents 8-Mbit Flash memory and

12697

Abstract: 80MHZ PM7326
Contextual Info: PM7326 S/UNI APEX RELEASED APPLICATION NOTE PMC-1991454 ISSUE 2 H/W PROGRAMMER’S GUIDE PM7326 TM S/UNI - APEX S/UNI-APEX ATM/PACKET TRAFFIC MANAGER AND SWITCH HARDWARE PROGRAMMER’S GUIDE RELEASED ISSUE 2: MARCH 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

M6MGB/T166S4BWG

Abstract: Mitsubishi Stacked CSP M6MGT166S4
Contextual Info: MITSUBISHI LSIs M6MG B/T166S4B WG 16,777,216-BIT 1,048,576 -WORD BY 16-BIT CMOS 3.3V-ONLY FLASH MEMORY & 4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) DESCRIPTION FEATURES The MITSUBISHI M6MGB/T166S4BWG is a Stacked Chip

Contextual Info: MITSUBISHI LSIs M6MGB/T160S2BVP 16,777,216-BIT 1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT CMOS 3.3V-ONLY FLASH MEMORY & 2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM Stacked-MCP (Multi Chip Package) DESCRIPTION FEATURES