O101 Search Results

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

Contextual Info: fax id: 6140 ^CYPRESS CY7C375Î UltraLogic 128-Macrocell Flash CPLD Features • • • • Functional Description 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

Contextual Info: • ■ J ^ m n r n n PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: PRELIMINARY C Y 7C 374i UltraLogic 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all l/Os and dedicated inputs

Contextual Info: Ordering number : EN694G 2SB815/2SD1048 Bipolar Transistor http://onsemi.com – 15V, (–)0.7A, Low VCE(sat), (PNP)NPN Single CP Features • • Ultrasmall package allows miniaturization in end products Large current capacity (IC=0.7A) and low-saturation voltage

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

65x2

Abstract: SED1530DAA SED1530T SED1530 SED1530D0 SED1530DA SED1530DF SED1531 SED1531D0 SED1532
Contextual Info: PF777-03 Series SED1530SED1530 Series Dot Matrix LCD Controller Driver SSC5000Series ● Ultra Low Power Consumption ● Built-in Power Supply Circuit for LCD ● 133 Driver Output • DESCRIPTION The SED1530 series is a single-chip LCD driver for dot-matrix liquid crystal displays LCD’s which is directly

Contextual Info: PRELIMINARY Cr CY37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET D S 0 7 -1 2 5 2 6 -1 E 8-bit Proprietary Microcontroller CM O S MB89923/925/P928/P V920 • DESCRIPTION The MB89920 series is a line of single-chip microcontrollers using the F2MC*-8L CPU core which can operate at low voltage but at high speed.

K 3673

Abstract: 3673 SN 46 LS 46 LC4103 LC4103C LC4103TAB-01 LC4103TAB-02
Contextual Info: * Ordering number:ENN 5193B CMOS P-sub LC4103TAB-01, 4103TAB-02, 4103C STN LCD Dot Matrix Common Driver Preliminary Overview The LC4103 is a common driver IC for large-scale dot matrix LCD displays, It includes a 160-bit bidirectional shift register and 4-level LCD drivers. The number of bits can

5d3 diode

Abstract: 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10
Contextual Info: MACH 5 CPLD Family I MAC ncludes H Adv anc 5A Fam e In form ily atio n Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os

ic 4040

Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

Ultra37128

Abstract: 37128VP100
Contextual Info: fax id: 6147 PRELIMINARY Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™ CPLD Features • High speed — fMAX = 125 MHz • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — tPD = 10 ns

tlp 453

Contextual Info: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant

Contextual Info: PREUM INAm Ultra37128V UltraLogic 3.3V 128-Macrocell ISR™CLPD — tPD = 10 ns Features — ts = 5.5 ns • 128 macrocells in eight logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

2A299

Abstract: HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND: -10/12/15/20 MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

MACH4 cpld amd

Abstract: mach 1 family amd HP3070
Contextual Info: MACH 4 FAMILY 1 MACH 4 Family High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ MACH 4 Family ◆ High-performance, EE CMOS CPLD family SpeedLocking for guaranteed fixed timing -7/10/12/15 ns tPD

marking 3B3

Abstract: 32V16 mach 1 family amd 3A10 MC5C1 MACH5 cpld amd
Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-256 MACH5-256/68-7/10/12/15/20 MACH5-256/104-7/10/12/15/20 MACH5-256/120-7/10/12/15/20 MACH5-256/160-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

MACH111SP

Abstract: MACH465 MACH4-256 mach4256
Contextual Info: MACH 4 FAMILY 1 FINAL COM’L: -10/12/15 IND:-12/14/18 MACH4-256/MACH4LV-256 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 208 pins in PQFP 256 macrocells 10 ns tPD Commercial, 12 ns tPD Industrial

dual-port RAM

Abstract: AT17 AT17LV010-10DP AT40K MQFPF256 IO358
Contextual Info: Features • Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series • Ultra High Performance • • • • • • • • • • • • • • – System Speeds 60 MHz – Array Multipliers > 32 MHz – 18 ns Flexible SRAM

MC189

Abstract: 9300 4b10 2D15 marking 1A15 HP 3D6 1b61a0 MACH5-320 ae 4b15
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-320/MACH5LV-320 MACH5-320/120-7/10/12/15 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15 MACH5-320/184-7/10/12/15

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes