XACU Search Results

ST188

Contextual Info: r z 7 Ä T# S C S -T H O M S O N & y i O T T M « S T 1 8 9 4 0 /4 1 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology ■ PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE ■ 3 DATA MODES . SINGLE PRECISION

YA128

Abstract: HDS-220 RCA 1A15 procesor P6E1 4x32 lcd BU 3150 MBS 6 B6 ST18 ST18941
Contextual Info: SGS-THOMSON ST18940/41 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology . PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE . 3 DATA MODES . SINGLE PRECISION . DOUBLE PRECISION . COMPLEX ■ 32-BIT INSTRUCTION

4 BIT ALU design with vhdl code using structural

Abstract: 8 BIT ALU design with vhdl code using structural arm piccolo 16 BIT ALU design structural 8 bit alu instruction in vhdl verilog code for 32 BIT ALU implementation vhdl code for speech recognition vhdl code for 8 bit barrel shifter vhdl code for alu low power vhdl code for FFT 32 point
Contextual Info: EMBEDDED DSP TECHNOLOGIES IN CONSUMER APPLICATIONS CLASS NOTES DSP WORLD WORKSHOPS SEPTEMBER 13-16 1998 TORONTO C.M. Moerman, R. Woudsma, P. Kievits Philips Semiconductors ASIC Service Group, Eindhoven, The Netherlands P.O. Box 218, 5600 MD Eindhoven, The Netherlands

EPR48

Abstract: LCD 2 x 16 ia87
Contextual Info: r = 7 Ä T # S G S - T H O M S O N R Æ Œ (ô m i(O T (ô K S S T 1 8 9 3 0 /3 1 DIGITAL SIGNAL PR O C ESSO R • 80 ns INSTRUCTION CYCLE TIME ‘ (1.2 (i CMOS technology) ■ PARALLEL HARVARD ARCHITECTURE ■ SEPARATED PROGRAM AND DATA BUSES ■ THREE DATA BUSES STRUCTURE

DSP320

Contextual Info: MICROCHIP TECHNOLOGY INC ESE D b I Q 3 2 Gl QG0SQ2M 2 DSP320C10 Microchip CMOS Digital Signal Processor DESCRIPTION FEATURES The DSP320C10 is the first low power CMOS member of the Microchip Technology DSP320 family of digital signal processors, designed to support a wide range of

ncl 071

Abstract: PGA121 4kx16 ram "saturation flag" INSTRUCTION SET motorola 6800 intel 68000 INSTRUCTION SET motorola 1031 PLCC52 24CCR 6800 intel microprocessor pin diagram
Contextual Info: SGS-THOMSON ¿ 5 7 IL itg T T ^ O R O D Ê S ST18930/31 DIGITAL SIGNAL PROCESSOR 80 ns INSTRUCTION CYCLE TIME ‘ 1.2 |i CMOS technology PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R/W OPERATION ON EX­

RRUS 01 B1

Abstract: RRUS 32 b2 RRUS 01 B2 ocular lcd e purse TS68930 TS68931 TSSB831 RRUS 01 3BS1
Contextual Info: T S 6 8 9 3 0 • T S 68931 ADVANCE INFORMATION HMOS2 The T S 6 8 9 3 0 /1 Programmable Signal Processor is a high-speed general purpose signal and arithm etic processor w ith on-chip memory, m ultiplier, ALU, accumulators and I/O s . It is organized in

Contextual Info: PRELIM INARY p i l C R Q ’ i! r\ v. '’ t- f M !. I i ü ü ? \ FLASH MEMORY h L. A b i ' 1 ’ IYIBG x rf i„IE i\,1 0 h V MT28F800B1 FEATURES • Eleven erase blocks: 16KB/8K-word boot block protected Two 8KB/4K-word parameter blocks Eight main memory blocks

RRUS 32

Abstract: RRUS 32 b2 RRUS 01 B1 RRUS 01 B2 2101S 68000 thomson
Contextual Info: fi?]> D S G S-THONSON 87D 08679 D § 7cl5cia37_DDDflt17c] r - i f j - n . o s - TS68930 • TS68931 ADVANCE INFORMATION HMOS2 The T S 68930/1 Programmable S ignal Processor is a high-speed general purpose signal and arithm etic processo'r w ith on-chip memory, m u ltip lier, ALU, accumulators and l/O s . It is organized in

3AD3

Abstract: barrel shifter block diagram intel 68000 INSTRUCTION SET lb 8930 TS68930 TS68931 block diagram for barrel shifter aos Manufacturing date code "saturation flag" xacu
Contextual Info: f Z 7 SGS-THOMSON m 7# [RÆQ g[i? iUi Tr^©[ïaO(gS TS68930/31 DIGITAL SIGNAL PR O C ESSO R 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R M OPERATION ON EX­

DAX 3S

Contextual Info: pro duct < £ 2 iL O B S pecificatio n Z89321/371/391 16-B it D ig it a l S ig n a l p r o c e s s o r s FEATURES Part DSP ROM K W ords O TP (K Words) DSP RAM (Words) MIPS (Max) 4 512 512 512 20 16 20 4 Z89321 Z89371 Z89391 64* Package Part Z89321 Z89371

lt074

Abstract: REGULATOR 0,12V 10A HL-AK147QQ LT1Q74 LT1074 LT1076 LT1076-5 MBR340 PE-92102 PE-92114
Contextual Info: um TECHNOLOGY Step-Down Switching Regulator tions allow this device to be used as a positive-to-negative converter, a negative boost converter, and as a flyback converter. The switch output is specified to swing 40V below ground, allowing the LT1074 to drive a tappedinductor in the buck mode with output currents up to 10A.

D347D

Abstract: ST18940 "saturation flag" 32 bit barrel shifter circuit diagram using multi
Contextual Info: f Z 7 SGS-THOMSON Ä 7 # O^D l^@llLli@¥l^@ß!lfl©i TS68930/31 DIGITAL SIGNAL PROCESSOR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE

MB88636

Abstract: MB8863 MB88636PF EZ 742 ez 948 MB88630 C1307-1 ez 948 ic st ez 650 EZ 830
Contextual Info: FUJITSU LTD S3E D H BTMTTSb QÜDBlbb T5T BIFCAJ March 1992 Edition 2.0 DATA SHEET F2MC -4L FAMILY MB88630 SERIES LOW POWER SINGLE-CHIP MICROCONTROLLER WITH LCD C/D AND ADC DESCRIPTION The Fiÿtsu MB88630 Sarin it a member of t o F*MC®-4L FamVy, and features a 32