ST18930 Search Results

ncl 071

Abstract: PGA121 4kx16 ram "saturation flag" INSTRUCTION SET motorola 6800 intel 68000 INSTRUCTION SET motorola 1031 PLCC52 24CCR 6800 intel microprocessor pin diagram
Contextual Info: SGS-THOMSON ¿ 5 7 IL itg T T ^ O R O D Ê S ST18930/31 DIGITAL SIGNAL PROCESSOR 80 ns INSTRUCTION CYCLE TIME ‘ 1.2 |i CMOS technology PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R/W OPERATION ON EX­

Contextual Info: r z 7 S C S -T H O M S O N « « L E M « ! _ T S 6 8 9 5 2 ^ 7# MODEM TRANSMIT/RECEIVE CLOCK GENERATOR • INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS ■ TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL

Contextual Info: ¿= 7 * > S G S -T H O M S O N J i. B ü il[ l g I [ L im ( M D ( g § T S 6 8 9 5 0 MODEM TRANSMIT ANALOG INTERFACE • TWO CHANNEL DIGITAL TO ANALOG CON­ VERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION ■ 6TH ORDER SWITCHED CAPACITOR LOW

ST188

Contextual Info: r z 7 Ä T# S C S -T H O M S O N & y i O T T M « S T 1 8 9 4 0 /4 1 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology ■ PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE ■ 3 DATA MODES . SINGLE PRECISION

YA128

Abstract: HDS-220 RCA 1A15 procesor P6E1 4x32 lcd BU 3150 MBS 6 B6 ST18 ST18941
Contextual Info: SGS-THOMSON ST18940/41 DIGITAL SIGNAL PROCESSOR MAIN FEATURES • 100ns MACHINE CYCLE TIME 1.2 CMOS Technology . PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE . 3 DATA MODES . SINGLE PRECISION . DOUBLE PRECISION . COMPLEX ■ 32-BIT INSTRUCTION

68951

Abstract: TS68951 BAT43 equivalent RC6 philips DIP28 PLCC28 TS68950 TS68951CFN TS68951CP TS68952
Contextual Info: TS68951 MODEM RECEIVE ANALOG INTERFACE . . . . . . . TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION WITH ASYNCHRONOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS PROGRAMMABLE SWITCHED CAPACITOR

ST189* instruction set

Abstract: "04503 st18 dela irc" ST18
Contextual Info: £ T 7 SGS-THOMSON ^7# M M e J C T (s « S _ ST18940/41 DIGITAL SIGNAL PROCESSOR A D V A N C E D A TA M A IN F E A T U R E S • 100ns MACHINE CYCLE TIME (1.2 CMOS Technology ■ PARALLEL HARVARD ARCHITECTURE ■ TRIPLE DATA BUSES STRUCTURE ■ 3 DATA MODES . SINGLE PRECISION

EPR48

Abstract: LCD 2 x 16 ia87
Contextual Info: r = 7 Ä T # S G S - T H O M S O N R Æ Œ (ô m i(O T (ô K S S T 1 8 9 3 0 /3 1 DIGITAL SIGNAL PR O C ESSO R • 80 ns INSTRUCTION CYCLE TIME ‘ (1.2 (i CMOS technology) ■ PARALLEL HARVARD ARCHITECTURE ■ SEPARATED PROGRAM AND DATA BUSES ■ THREE DATA BUSES STRUCTURE

fsk arm dtmf

Abstract: SCR c106 PIN CONFIGURATION active tone control circuit with TL072 scr C106 DIP28 DIP48 PLCC28 PLCC52 c19f TS7538
Contextual Info: TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET . . . . . . . . . . . . . . . . . ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICATIONS

DSP/teaklite 3 instruction opcode

Contextual Info: r i j S G S -T H O M S O N *7 M TS75C32 V.32, V.22bis, V.22, V.23, V.21, BELL 212A, BELL 103 MODEM CHIP SET ADVANCE DATA • CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIPSET ■ INTEGRATED IMPLEMENTATION ON THREE DSP AND THREE MAFE CHIPS

Contextual Info: ¿ = 7 S C S -T H O M S O N *JÆ, 6aiD g ®IlL[I irMDȧ TS68951 MODEM RECEIVE ANALOG INTERFACE • TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION (WITH ASYNCHRO­ NOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS

TS7538

Abstract: SDS S4 24V TS7532 0-600C SDS S4 - 24V
Contextual Info: TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET . . . . . . . . . . . . . . . . . ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICATIONS

Contextual Info: TS68950 MODEM TRANSMIT ANALOG INTERFACE TWO CHANNEL DIGITAL TO ANALOG CONVERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION 6TH ORDER SWITCHED CAPACITOR LOW PASS FILTER FOR ADAPTATION TO THE TELEPHONE BANDWIDTH OUTPUT CONTINUOUS TIME SMOOTHING

DIP28

Abstract: PLCC28 TS68950 TS68951 TS68952 TS68952CFN TS68952CP programming controle system with c rc711
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

Contextual Info: S. ? 1993 /= T #. ^7 S C S -T H O M S O N HKSW M S 5 TS 7538 ASYNCHRONOUS-SYNCHRONOUS AND SERIAL-PARALLEL CONVERTER • . . ■ ■ ■ ■ . ■ ■ ■ BOTH ASYNCH R O N O U S AND SYNCHRO­ NOUS M O DES OF OPERATION INCLUDING FULL CCITT V.14 ARHYTHM IC CHARAC­

Contextual Info: 0011103 1 ‘" P 7 5 ^ 2 -O S S G S -T H O M S O N * TS75C25 t 7 V.22 BIS, V.22, BELL 212, V.21 V.23, BELL 103 M O D EM C H IP SET ADVANCE DATA • CCITT V.22 BIS COMPATIBLE MODEM CHIP of modems complying with CCITT V.21, V.22, V.23, SET and BELL 103, 212 recommendations. The modem

Contextual Info: I S G S -T H O M S O N ¿ 5 7 TS68951 me MODEM RECEIVE ANALOG INTERFACE TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION with asynchronous multiplexing of 2 plesiochronous channels

3AD3

Abstract: barrel shifter block diagram intel 68000 INSTRUCTION SET lb 8930 TS68930 TS68931 block diagram for barrel shifter aos Manufacturing date code "saturation flag" xacu
Contextual Info: f Z 7 SGS-THOMSON m 7# [RÆQ g[i? iUi Tr^©[ïaO(gS TS68930/31 DIGITAL SIGNAL PR O C ESSO R 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE DUAL EXTERNAL BUSES ONE CYCLE 16-BIT R M OPERATION ON EX­

2900Hz

Abstract: Polarised capacitor rr1 440
Contextual Info: TS68951 MODEM RECEIVE ANALOG INTERFACE . . . . . . . TWO CHANNEL 12-BIT ANALOG TO DIGITAL CONVERTER FOR RECEPTION OF DIGITAL DATA FROM THE TELEPHONE LINE AND ECHO CANCELLATION WITH ASYNCHRONOUS MULTIPLEXING OF 2 PLESIOCHRONOUS CHANNELS PROGRAMMABLE SWITCHED CAPACITOR

V27bis

Abstract: 68950 PLCC28 TS68950 TS68950CFN TS68950CP TS68951 TS68952 V26BIS modem circuit echo
Contextual Info: TS68950 MODEM TRANSMIT ANALOG INTERFACE TWO CHANNEL DIGITAL TO ANALOG CONVERTER FOR TRANSMISSION OF DIGITAL DATA TO THE TELEPHONE LINE AND ECHO CANCELLATION 6TH ORDER SWITCHED CAPACITOR LOW PASS FILTER FOR ADAPTATION TO THE TELEPHONE BANDWIDTH OUTPUT CONTINUOUS TIME SMOOTHING

TDC 8117

Abstract: TS68952CP
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

SDS st2

Abstract: 32QAM BLOCK DIAGRAM SGS-THOMSON modem DIP28 DIP48 PLCC28 PLCC52 TS75C32 TS75C320CP DTMF DEcoder i2c
Contextual Info: TS75C32 V.32, V.22bis, V.22, V.23, V.21, BELL 212A, BELL 103 MODEM CHIP SET CCITT V.32, V22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET INTEGRATED IMPLEMENTATION ON THREE DSP AND THREE MAFE CHIPS FULL DUPLEX OPERATION FROM 9600 TO 300BPS

D347D

Abstract: ST18940 "saturation flag" 32 bit barrel shifter circuit diagram using multi
Contextual Info: f Z 7 SGS-THOMSON Ä 7 # O^D l^@llLli@¥l^@ß!lfl©i TS68930/31 DIGITAL SIGNAL PROCESSOR • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 160ns INSTRUCTION CYCLE TIME PARALLEL HARVARD ARCHITECTURE SEPARATED PROGRAM AND DATA BUSES THREE DATA BUSES STRUCTURE

tsl usc1

Abstract: HD7x BL342
Contextual Info: S G S -T H O M S O N TS75C96 V.32, V.29, V.27ter, V.22bis, V.22, V.23, BELL 212A, BELL 103 MODEM CHIP SET ADVANCE DATA CCITT V.32, V.22bis, V.22, V.21, V.23, Bell 212A, Bell 103 COMPATIBLE MODEM CHIP SET CCITT V.29, V.27ter FOR FAX APPLICA­ TIONS INTEGRATED IMPLEMENTATION ON THREE