WIDTH11 Search Results

Contextual Info: INTEGRATE» DEVICE bbE D • 4BES771 □ □ 1 2 M cn CMOS SyncFIFO 64x8, 256x8,512x8, 1024 x 8, 2048 x 8 and 4096 x 8 715 « I D T IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 FEATURES: DESCRIPTION: • • • • • • • • • T he ID T 7 2 4 2 0 /7 2 2 0 0 /7 2 2 1 0 /7 2 2 2 0 /7 2 2 3 0 /7 2 2 4 0

Contextual Info: DENSE-PAC 256Kx8 FLASH/32Kx8 SRAM Combo Memory Mi C R OSYSTE MS DP59CF232 K DESCRIPTION: The DP59CF232K is a combination memory chip consist of 2M-bit Flash Memory organized as 256K words by 8 bits and a 256K-bit Static Random Access Memory organized as 32K words by 8 bits.

72V841

Contextual Info: 3.3 VOLT DUAL CMOS SyncFlFO DUAL 256 X 9, DUAL 512 X 9, DUAL 1,024 X 9, DUAL 2,048 X 9 and DUAL 4,096 X 9 Each of the two FI FOs designated FI FO A and FI FO B contained In the IDT72V801 /72V811/72V821 /72V831 /72V841 has a 9-bit input data port (DAO - DA8, DB0 - DB8) and a9-blt output data port (QA0 -QA8, QB0 - QB8).

bitblt raster

Abstract: NS32FX16 bitblt AN-634 C1995
Contextual Info: National Semiconductor Application Note 634 July 1990 1 0 INTRODUCTION The NS32CG16 has several instructions that automate the process of performing a BIT aligned BLock Transfer BITBLT In this application note the parameter setup for these instructions will be discussed The NS32FX16 is pin

Contextual Info: UTOPIAFIFO PRELIMINARY INFORMATION 1 TO 4 IDT77301 128 X 9 X 4 DEMULTIPLEXER-FIFO Integrated Device Technology, Inc. FEATURES: GENERAL DESCRIPTION • • • • • • • • • • • • • • The IDT77301 UtopiaFlFO is a high-speed, low power

variable ramp generator

Contextual Info: a FEATURES Single +5 V Supply TTL and CMOS Compatible 10 ps Delay Resolution 2.5 ns to 10 ␮s Full-Scale Range Maximum Trigger Rate 50 MHz MIL-STD-883-Compliant Versions Available Digitally Programmable Delay Generator AD9501 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS

Contextual Info: t InNET TECHNOLOGIES T0468S Electrical REV. X E L E C T R IC A L S P E C IF IC A T IO N S TURNS RATIO: (TXIN+)—(CTIN)—(TXIN—) : (TXO+)-(CTO)-CTXO-) 1.25CT : 1CT ± 3% (RXO+)—(RXO—) : (RXIN+)—(RXIN—) 1 : 1 ± 3% R X 1+<D_i^rH|if— INDUCTANCE:

42XS-3

Contextual Info: fax id: 5410 CY7C4425/4205/4215 _ CY7C4225/4235/4245 "64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Features controlled by a free-running clock WCLK and a write enable pin (WEN). • High-speed, iow-power, first-in first-out (FIFO) memories

LR33300

Abstract: LR33310 J14028 LR3330 2 TZ 11w LR33300MC20 LSI DP3 LR33310MC lr3331 lsi lr33310
Contextual Info: LR33300 and LR33310 Self-Embedding Processors User’s Manual LSI LOCK Addendum Addendum Number A000379 Order Number for Manual J14028 Introduction This addendum to the LR33300 and LR33310 Self-Embedding Proces­ sors User’s Manual specifies the LR333xO’s electrical and mechanical

C30844

Abstract: C30845 rca 632 quadrant photodiode rca C30846 quadrant photodiode 303dbl0 92LS-S56S "S56S" PIN quadrant detector
Contextual Info: RC/1 E G & G/CA N A D A / O P T OELEK 3G30fc.lD ODOOIDI Tfl4 « C A N A IO Electro Photodiode C30843 Optics C30844, C30845, C30846 DATA SHEET Quadrant N-Type Silicon p-i-n Photodetectors • Broad Range of Photosensitive Suface Areas — 5 mm2 to 100 mm2 ■ Low Operating \foltage —

schematic diagram tv sony kv 2197

Abstract: scheme tv color tucson LOG100 ADC600 ISO106 sony ccd ADC-817 adc817 SDM857 SHC76
Contextual Info: HOW TO USE THIS BOOK If you know the MODEL NUMBER, Use the Model Index on the INSIDE FRONT COVER. If you know the PRODUCT TYPE, Use the TABBED TABLE OF CONTENTS on page v. Or, use the SELECTION GUIDE TABLES at the front of each tabbed section. If you know the M ODEL

Contextual Info: B U R R -B R O W N S [ ADC80MAH-12 1 AVAILABLE IN DIE FORM Monolithic 12-Bit ANALOG-TO-DIGITAL CONVERTER reduced resolution, and an external clock may be used to synchronize the converter to the system clock or to obtain higher-speed operation. The convert

18CV8

Abstract: 18CV825 18CV815 18cv8 programming 18CV8-15 HAS64 PEEL18CV8 AMI PEEL18CV8
Contextual Info: AMI PEEL 18CV8 SEMICONDUCTORS February 1993 CMOS Programmable Electrically Erasable Logic Device General Description Features The AMI PEEL18CV8 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

l 9143

Abstract: c80m
Contextual Info: BURR-BROWN CORP h e » Ii7 3 i3 ts onm sia " T ' ^ l -\o n I -\7- ~ ADC80MAH-12 B U R R -B R O W N S •1=3EE3 3 A V A IL A B L E IN D IE FO RM Monolithic 12-Bit ANALOG-TO-DIGITAL CONVERTER reduced resolution, and an external clock may be used to synchronize the converter to the system clock

Contextual Info: A im • P EEL 18CV8L STANDARD PRODUCTS American Microsystems, Inc. March 1994 CMOS Programmable E lectrically Erasable Logic Device Features General Description The AMI PEEL18CV8L is a low voltage CMOS Programmable Electrically Erasable Logic device that

Contextual Info: SAMSUNG ELECTRONICS INC KM75C102A H2E D B 7=1^4142 OD112S1 3 BSM'fiK CMOS PROGRAMMABLE FLAG FIFO " T - i4! ''3>S Programmable-Flags, 1KX9 FIFO FEATURES DESCRIPTION • First-ln-First-Oiit Dual Port Memory —1K x 9 Organization • Very High Speed Independent of depth/width

variable ramp generator

Abstract: Knock AD9501 AD9501JN AD9501JP AD9501JQ AD9501SQ digital delay generator
Contextual Info: a FEATURES Single +5 V Supply TTL and CMOS Compatible 10 ps Delay Resolution 2.5 ns to 10 ␮s Full-Scale Range Maximum Trigger Rate 50 MHz MIL-STD-883-Compliant Versions Available Digitally Programmable Delay Generator AD9501 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS

18CV825

Abstract: PEEL18CV8 AMI 18CV8 18cv8 programming ami equivalent gates ami equivalent gates of each core cell PEEL18CV8 18CV8-15
Contextual Info: PEEL 18CV8 AMI SEMICONDUCTORS CMOS Programmable Electrically Erasable Logic Device February 1993 General Description Features The AMI PEEL18CV8 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

22-25L

Abstract: 22-35L 2235L
Contextual Info: CMOS SyncFIFO ID T 7 2 2 0 5 L B ID T 7 2 2 1 5 L B ID T 7 2 2 2 5 L B ID T 7 2 2 3 5 L B ID T 7 2 2 4 5 L B 2 5 6 X 18, 5 1 2 X 1 8 ,1 0 2 4 x 18, 2 0 4 8 x 18 a n d 4 0 9 6 x 1 8 FEATURES: Both FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock WCLK , and a data

56c55

Contextual Info: IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB CMOS SyncFlFO 256 X 18, 512 X 18,1024 x 18, 2048 x 18 and 4096 x 18 Integrated D evice Technology, Inc. FEATURES: Both FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock WCLK , and a data

18CV8

Abstract: 18CV8-15 18CV815 ami equivalent gates 18CV825 PEEL18CV8
Contextual Info: PEEL 18CV8 AMI SEMICONDUCTORS February 1993 CMOS Programmable Electrically Erasable Logic Device Features General Description The AMI PEEL18CV8 is a CMOS Programmable Electrically Erasable Logic device that provides a highperformance, low-power, reprogrammable,

Contextual Info: W LÆPER^Ê C O ÌV I T V PI74FCT821T/823T/825T 25Í2 Series PI74FCT2821T/2823T Fast CMOS Bus Interface Registers Product Features: • P I74F C T 821T /823T /825T /2821T /2823T is pin com patible with bipolar FA ST Series at a higher speed and low er

T0459S

Contextual Info: InNET TECHNOLOGIES te c lln o ^ ^ e j j 3 t T0459S Electrical E L E C T R IC A L S P E C IF IC A T IO N S (REV. X TURNS RATIO: (T X IN + )-(T C T I N ) -C lX IN -) : ( T X O + ) -(T C T O )-( T X O -) 1CT : 1CT ± 3 * (RXO+)—(RCTO)—(RXO—) : (RXIN+)-(RCTIN)-(RXIN-)

3QA18

Contextual Info: 256Kx8 FLASH/32Kx8 SRAM Combo Memory DP59CF232 M í C \i O S Y S T E M S DESCRIPTION: The DP59CF232 is a combination memory chip consist of 2M-bit Flash Memory organized as 256K words by 8 bits and a 256K-bit Static Random Access Memory organized as 32K words by 8 bits.