VTERM Search Results

Contextual Info:  LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Delete Icc1 Spec. Added I Grade Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2

LY61L12816

Contextual Info:  LY61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issued Revised PACKAGE OUTLINE DIMENSION Revised VTERM to VT1 and VT2 Revised Test Condition of ICC/ISB1/IDR

ly62l256

Contextual Info:  LY62L256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Revised STSOP Package Outline Dimension Deleted L Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR

Contextual Info: LY61L12816 128K X 16 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issued Revised PACKAGE OUTLINE DIMENSION Revised VTERM to VT1 and VT2 Revised Test Condition of ICC/ISB1/IDR

Contextual Info: LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.5 Description Initial Issue Delete Icc1 Spec. Add E/I grade Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec.

49-LEAD

Abstract: ADATE209
Contextual Info: FEATURES >4.0 Gbps 2 V swings 120 ps rise time/fall time (2 V swings) <1.0 W for dual driver (<500 mW/channel) −1 V to +3.5 V range Fast VTERM Cable loss compensation FUNCTIONAL BLOCK DIAGRAM VH1 VL1 VT1 DA1 CLC1EN VH2 APPLICATIONS Automatic test equipment

ene kb3310qf c1

Abstract: kb3310qf c1 ene kb3310qf a0 ene kb3310qf b0 MB39A129 ene kb3310 KB3310 kb3310qf ene kb3310qf RTM875T-606
Contextual Info: 5 4 3 2 1 2008.06.01 D C Mariana Block Diagram VTERM +0.9V C Stage VTT(+1.05V) +1.5VSUS CPU VCORE VID[0:6] XDP Diamondville +1.5V IMVP 6 +1.8VSUS FCBGA8 437 +1.8V +/- CPU_CLK VCORE:+1.196 ~ +0.748 VCCP:+1.05V Thermal Clock Gengerator +2.5V VCCA:+1.8V or +1.5V

K7P161866A

Abstract: K7P161866A-HC25 K7P161866A-HC30 K7P161866A-HC33 K7P163666A K7P163666A-HC25 K7P163666A-HC30 K7P163666A-HC33 SA13 SA18
Contextual Info: K7P163666A K7P161866A 512Kx36 & 1Mx18 SRAM Document Title 512Kx36 & 1Mx18 Synchronous Pipelined SRAM Revision History Draft Date Remark - Initial Document Dec. 2001 Advance - Absolute maximum ratings are changed VDD : 2.815 - > 3.13 VDDQ : 2.815 - > 2.4 VTERM : 2.815 - > VDDQ+0.5 2.4V MAX

Contextual Info: LY61L1024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 2.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Rev. 2.1 Rev.2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Description Initial Issue Delete Icc1 Spec. Adding -10ns Spec. Revised VTERM to VT1 and VT2

Contextual Info: LY61L256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec. Revised Test Condition of ICC/ISB

Contextual Info: LY612568 5V 256K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Description Preliminary Revised Test Condition of ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package

Contextual Info: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.4 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2

Contextual Info: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2

Contextual Info:  LY61L256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec. Revised Test Condition of ICC/ISB

LY62W10248

Contextual Info:  LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Added ISB Spec. Revised ICC1/ISB1/VDR/IDR Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR

RAC RAMBUS

Abstract: RDRAM CONCURRENT concurrent rdram rdram concurrent 72M concurrent RDRAM 72 OF800 concurrent rdram NEC
Contextual Info: NEW PRODUCTS 3 72M-BIT DIRECT RAMBUS DRAM RDRAM µPD488385 Masuo Furuta Vdd Gnd Vref Low-speed bus SIN RAC Controller SOUT SIN RDRAM No.1 VTERM SOUT RDRAM No.n Bus Data Control High-speed bus Receive clock Transmit clock Clock Driver Fig. 1 Outline of Rambus System

LY611024

Contextual Info:  LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Delete Icc1 Spec. Add E/I grade Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR

Contextual Info:  LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Added ISB Spec. Revised ICC1/ISB1/VDR/IDR Spec. Revised VTERM to VT1 and VT2

Contextual Info: LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Delete Icc1 Spec. Added I Grade Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2

Contextual Info: LY61L2568 256K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Rev. 0.3 Rev. 0.4 Rev. 0.5 Rev. 0.6 Rev. 1.0 Description Preliminary Deleted ISB Spec. Deleted -10/-12/-15 Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2

Contextual Info: LY615128 5V 512K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Description Initial Issue Revised Package Outline Dimension TSOP-II Revised VTERM to VT1 and VT2 Revised Test Condition of ICC/ISB1/IDR

Contextual Info: LY62L5128 512K X 8 BIT LOW POWER CMOS SRAM Rev. 1.2 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Deleted L Spec. Added SL Spec. Revised VTERM to VT1 and VT2

Contextual Info: II 12 10 9 7 8 6 1 71477 3 1 2 NOTES? L INSULATOR? GL AS S F I L L E D POLYMER, U.L . 94 VTERMINAL? PHOSPHOR BRONZE. COLOR? BLA CK . 2. CONFORMS TO PRODUCT S P E C . 7 0 9 2 8 . 3. PA RT TO BE PACKAGED PER P K - 7 0 8 7 3 - 0 6 0 3 . NOTE FOR LEAD F R E E CONVERSION^

kb3310qf c1

Abstract: KB3310QF mmc ga201 KB3310 kb3310qf b0 quanta at2 KB3310QF-B0 AOZ1021 quanta at1 quanta
Contextual Info: 5 D 4 VTERM +0.9V VTT(+1.05V) +1.5VSUS +1.5V +1.8VMEM +1.8V +2.5V 3VPCU +3.3V +3.3VSUS LCD_3.3V LCD_5V +5V 3 2 IL1 Block Diagram B -> C 2008-01-08 VID[0:6] C7-M (ULV) VCORE:+1.196 ~ +0.748 VCCP:+1.05V VCCA:+1.8V or +1.5V +/- CPU_CLK +/- HCLK CRT 256M/512M/1GB