LY612568 Search Results

Contextual Info: LY612568 5V 256K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.0 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Description Preliminary Revised Test Condition of ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package

Contextual Info: LY612568 5V 256K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 0.2 REVISION HISTORY Revision Rev. 0.1 Rev. 0.2 Description Preliminary Revised Test Condition of ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package

Contextual Info: LY612568 5V 256K X 8 BIT HIGH SPEED CMOS SRAM Preliminary 0.1 REVISION HISTORY Revision Rev. 0.1 Description Preliminary Issue Date Dec.6.2006 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

CS16LV40963

Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Contextual Info: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D

Contextual Info: LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Description Initial Issue Delete Icc1/ ISB Spec. Adding Skinny P-DIP Revised STSOP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice.

Contextual Info: Page:1/1 Update: January 9, 2015 High Speed SRAM Density 64K Configuration 8K x 8 Power Supply 5V 5V 256K Item No. Speed ns LY6164 Isb 12/15 1.0mA(typ) LY61256 12/15 0.5mA(typ) Operating Temp. (*1) Data Sheet C/E/I C/E/I 32K × 8 3.3V LY61L256 12/15 0.5mA(typ)

ly61256dl

Contextual Info: LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.8 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Rev. 1.8 Description Initial Issue Delete Icc1/ ISB Spec. Adding Skinny P-DIP Revised STSOP Package Outline Dimension

ly61256

Contextual Info:  LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Description Initial Issue Delete Icc1/ ISB Spec. Adding Skinny P-DIP Revised STSOP Package Outline Dimension Revised VTERM to VT1 and VT2

LY61256

Contextual Info: LY61256 32K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 FEATURES GENERAL DESCRIPTION „ Fast access time : 8/10/12/15ns „ Low power consumption: Operating current : 110/100/90/80mA TYP. Standby current : 1mA (TYP.) „ Single 5V power supply „ All inputs and outputs TTL compatible