SPARTAN XC2S50
Abstract: XCS10 vq100 FG456 XC2S50 xilinx CS144 CSP144 CS144 xc2s30 pq208 XCS30 PQ208 XC2S15
Text: High volume package solutions guide partanTM families provide the low-cost, high-volume ASIC packages for applications that need low power, small form factors and high reliability. The Chip Scale Package CSP and the Fine Pitch BGA package (FG) provide higher
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Actel
Abstract: CMOS OR Gates vq 44 quad flatpack 44 pin actel
Text: Addendum Accelerator Series FPGAs – ACT 3 Family The Ordering Information was updated to include RoHS information. A114100 A _ 1 RQ G 208 C Application Temperature Range C = Commercial (0 to +70˚C) I = Industrial (–40 to +85˚C) M = Military (–55 to +125˚C)
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A114100
MIL-STD-883
5172106AD-0/6
Actel
CMOS OR Gates
vq 44 quad flatpack
44 pin actel
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Actel A1020
Abstract: a1020 transistor ACTEL A1010 a1020 transistor a1020 Actel part number A1010 actel Actel a1020 datasheet A1020 semiconductor
Text: Addendum ACT 1 Series FPGAs The Ordering Information was updated to include RoHS information. B A1010 _ 2 PL G 84 C Application Temperature Range C = Commercial (0 to +70˚C) I = Industrial (–40 to +85˚C) M = Military (–55 to +125˚C) B = MIL-STD-883
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A1010
MIL-STD-883
5172102AD-0/6
Actel A1020
a1020 transistor
ACTEL A1010
a1020
transistor a1020
Actel part number
A1010 actel
Actel
a1020 datasheet
A1020 semiconductor
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transistor A1010
Abstract: actel a1020b actel a10v20b A1020b
Text: BACK ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates
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20-Pin
84-Pin
A1020B
transistor A1010
actel a1020b
actel a10v20b
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A1020B
Abstract: a1010b transistor a1020 A1010 A1020 transistor A1010
Text: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates
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A1010B
A10V10B
A1020B
A10V20B
84-Pin
84-Pin
A1020B
a1010b
transistor a1020
A1010
A1020
transistor A1010
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A1010
Abstract: A1010B A1020 A1020B transistor A1010
Text: ACT 1 Series FPGAs • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates
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A1020B
A10V20B
84-Pin
A1020B
84-Pin
A1010
A1010B
A1020
transistor A1010
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Untitled
Abstract: No abstract text available
Text: Component Selector Guide 5 V o lt C o m p o n e n t S e le c t o r G u id e Flip-Flops Device Pkg1 A1010B PG PL A1020B A1225A A1225XL* A1240A A1240XL* Speed Option2 Temp.3 User I/O 84 Std, -1 C, M, B 57 1,200 44 Std, - 1 , - 2 , -3 C, I 34 1,200 C, I 57 1,200
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A1010B
A10V20B
A14V15A
A14V25A
A14V40A
A14V60A
A14V100A
MIL-STD-883C
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UPD23C2000
Abstract: 33AO nec 40-pin plastic dip
Text: N Hi fiPD23C2000 2,097,152-Bit Mask-Programmable CMOS ROM Description Pin Configurations Th e ftP D 23 C 200 0 is a 2,097,152-bit ROM fab ricated with C M O S siiicon-gate technology. T h e device is static in operation and can be organized as 131,072 w ords by 16
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uPD23C2000
152-Bit
PD23C2000
fPD23C2000
pPD23C2000
33AO
nec 40-pin plastic dip
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Untitled
Abstract: No abstract text available
Text: ACT 1 Series FPGAs Features • A security fuse may be programmed to disable all further programming and to protect the design from being copied or 5Vand 3.3V Fam iliesfully compatible with JEDEC reverse engineered. specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates
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20-Pin
A1010B
A10V10B
A1020B
A10V20B
84-Pin
90S-1
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UPD23C2000
Abstract: No abstract text available
Text: JJPD23C2000 2,097,152-Bit Mask-Programmable CMOS ROM Description Pin Configurations Th e fiP D 23 C 2 000 is a 2,097,152-bit ROM fab ricated w ith C M O S silicon-gate technology. Th e device is static in operation and ca n be organized as 131,072 w ords by 16
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uPD23C2000
152-Bit
JJPD23C2000
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23C2000
Abstract: UPD23C2000 D23C2000c pd23c2000 2000C TIL 100 d23c2000
Text: JJPD23C2000 2,097,152-Bit Mask-Programmable CMOS ROM Pin Configurations The ftPD23C2000 is a 2,097,152-bit ROM fabricated with CMOS silicon-gate technology. The device is static in operation and can be organized as 131,072 words by 16 bits word configuration or as 262,144 words by 8 bits
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uPD23C2000
152-Bit
40-Pin
ftPD23C2000
iiPD23C2000
jLfPD23C2000
23C2000
D23C2000c
pd23c2000
2000C
TIL 100
d23c2000
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A1010B
Abstract: A1020B A1010 A1020 DN241 actel a1020b actel a10v20b ACTEL A1010 LL HP A1010-PL
Text: Æ 9 c t§ Ê • ACT 1 Series FPGAs Features A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. P ro d u c t F a m ily P ro file • Replaces up to 50 TTL Packages A 1010B
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20-Pin
84-Pin
A1020B
A1010B
A1010
A1020
DN241
actel a1020b
actel a10v20b
ACTEL A1010
LL HP
A1010-PL
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A1010-PL
Abstract: Microsoft 007 ird
Text: ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. • Up to 2000 Gate Array Gates 6000 PLD equivalent gates
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20-Pin
10Kresistor
A1020B
A1010-PL
Microsoft 007 ird
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Untitled
Abstract: No abstract text available
Text: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- J M N K ♦ t t < ij / 5; PRELIMINARY *^ ' CY37064 UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tco = 4.5 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ (ISR™
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CY37064
64-Macrocell
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY CY37128 UltraLogic 128-Macrocell ISR™ CPLD Features • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes
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CY37128
128-Macrocell
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Untitled
Abstract: No abstract text available
Text: ” / C Y P R E S S C Y 7 < M UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology
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64-Macrocell
CY7C373i
ASH370iTM
ASH370i
22V10,
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Untitled
Abstract: No abstract text available
Text: CY7C132/CY7C136 CY7C142/CY7C146 if CYPRESS 2K x 8 Dual-Port Static RAM Functional D escription Features • 0.8-raicron CMOS for optimum speed/ power • BUSY output flag on CY7C132/ CY7C136; BUSY input on CY7C142/CY7C146 The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8
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CY7C132/CY7C136
CY7C142/CY7C146
CY7C132/
CY7C136;
CY7C132/CY7C136/CY7C142
CY7C146
CY7C136
CY7C142/CY7C146
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Untitled
Abstract: No abstract text available
Text: CY7C960 CY7C961 Low Cost VMEbus Interface Controller Family Features Functional Description • 80-Mbyte-per-second block transfer rates • All VME64 transactions provided, including A64/D64, A40/MD32 transfers • Auto Slot ID • CR/CSR space • All standard Rev C VMEbustransactions implemented
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CY7C960
CY7C961
80-Mbyte-per-second
VME64
A64/D64,
A40/MD32
64-pin
CY7C960)
100-pin
14x14mm
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Untitled
Abstract: No abstract text available
Text: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JMNK ♦ PRELIMINARY t t *^ ' < ij / 5; CY37064 UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — tco = 4.0 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ (ISR™ JTAG-compliant
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CY37064
64-Macrocell
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Untitled
Abstract: No abstract text available
Text: — > 1 ! i Features Product Summary fcM Figure 1 • Partial View o f an ACT 1 Device A C T 1 D e v ic e S tru c tu re A partial view of an ACT 1 device Figure 1 depicts four logic modules and distributed horizontal and vertical Interconnect tracks. PLICE antifuses, located at intersections of the
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DDD136T
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CY37128P84-125JI
Abstract: No abstract text available
Text: UltraLogic 128-Macrocell ISR™ CPLD Features • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes
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128-Macrocell
CY37128P84-125JI
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Untitled
Abstract: No abstract text available
Text: TL16C754 QUAD UART WITH 64-BYTE FIFO SLLS279 - SEPTEMBER 1998 ST16C654 Pin Compatible With Additional Enhancements Supports 2.92 Mbps 35-MHz Input Clock Baud Rates 64-Byte Transmit FIFO Software Selectable Baud Rate Generator Prescalable Clock Rates of 1X and 4X
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TL16C754
64-BYTE
SLLS279
ST16C654
35-MHz
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Untitled
Abstract: No abstract text available
Text: Actel Mask Programmed Gate Arrays F e a tu re s D e s c rip tio n Mask Programmed versions of Actel Field Programmable Gate Arrays FPGAs Significant cost reduction for medium- to high-volume applications Pin-for-pin compatible with Actel FPGAs PCI Local Bus Revision 2 Compliant
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M1440
176-Pin
011241b
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Untitled
Abstract: No abstract text available
Text: . „ n « PRELIMINARY Ultra37128 UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 128 macrocells in eight logic blocks • In-System Reprogram mable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes
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Ultra37128
128-Macrocell
IEEE1149
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