VLLB Search Results

IC HXJ 2038

Abstract: 1N52398 DB5T tfk 102 cny 70 hxj 2038 rca 40361 transistor rca 40362 TFK 680 CNY 70 Diode Equivalent 1N34A 2n5952 equivalent
Contextual Info: The Engineering Staff of TEXAS INSTRUMENTS INCORPORATED Components Group The T ransistor and Diode Data Book for Design Engineers T e x a s In s t r u m e n t s IN CO RPO RATED TYPE NUMBER INDEX GLOSSARY TRANSISTOR SELECTION GUIDES TRANSISTOR INTERCHANGEABILITY

LM373

Abstract: MC1303L LM566 "direct replacement" transistor BD 540 LYS MFC6030 LM566 equivalent LM3039 SN72558P LM370 SN72741P
Contextual Info: Edge Index by Product Family Here is the new Linear Data Handbook from National. It gives complete specifications for devices useful in building nearly all types of electronic systems, from communica­ tions and consumer-oriented circuits to precision instrumentation and computer designs.

TA8502F

Abstract: TA8512F TC8607F
Contextual Info: TOSHIBA UC/UP t»4E D • Q Q a b ^ l 11! Tlfi ■ T0S3 FLOPPY DISK MECHANISM CONTROLLER 11 TC8607F Floppy Disk M echanism Controller 1. G ENERAL DESCRIPTION 45 31 1 15 TC8G07F is a single chip C-MOS LSI for the floppy disk drive digital control logic, consisting

motorola 12514

Contextual Info: ^ M O T O R O L A Military 12511 Two Modulus Prescaler ELECTRICALLY TESTED PER: MPG 12511 The 12511 is a two-modulus prescaler which will divide by 8 and 9. A MECL-toMTTL translator is provided to interface with the 12514 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source.

100A484

Abstract: 101A48 IDT10484 ECL-10K IDT100A4M 4Kx4 SRAM
Contextual Info: r — I N T E G R A T E D DE VICE 3ÔE D • 4 Ô 2 S771 D Ü 0 b071 4 DÉ IDT 3 > '0 < Z HIGH-SPEED BiCMOS ECL STATIC RAM 16K 4K x 4-BIT SRAM PRELIMINARY IDT10A484 IDT100A434 IDT101A484 FEATURES; DESCRIPTION: • • ■ • • • • • The IDT10A484,1DT100A484 and IDT101A484 are 16,384bit high-speed BiCEMOS ECL static random access

Contextual Info: in U T M51C64HL HIGH PERFORMANCE LOW POWER RIPPLEMODETM 64K x 1 CHMOS DYNAMIC RAM Military M51C64HL-12 120 Maximum Access Time ns Maximum Column Address Access Time (ns) Maximum CHMOS Standby Current (mA) 65 0.05 R ip p le m o d e T M Operation — Continuous Data Rate over 13 MHz

CD4024

Abstract: diagrams VW ecu 100474 LS000262
Contextual Info: Am100474 1 0 2 4 x 4 IMOX ECL Bipolar RAM Am100474 PRELIMINARY DISTINCTIVE CHARACTERISTICS • • • Fast access time 10 ns — improves system cycle speeds. Fully com patible with 100K series ECL logic — no board changes required. Enhanced output voltage level compensation providing

270033

Abstract: Teac A 3440 M51C64HL M51C64HL-12 M51C64HL-15
Contextual Info: in U T M51C64HL HIGH PERFORMANCE LOW POWER RIPPLEMODE tm 64K x 1 CHMOS DYNAMIC RAM Military M51C64HL-12 M51C64HL-15 150 75 0.05 120 Maximum Access Time ns Maximum Column Address Access Time (ns) Maximum CHMOS Standby Current (mA) 65 0.05 m RipplemodeTM Operation

HN462532G

Abstract: HN462732G HN4827128G-25 6116ALSP-15 482732AG 6116LP 613128P HM4816AP4 6116ALP-10 HM4816AP-4
Contextual Info: \ HITACHI IC MEMORY DATA BOOK 0 HITACHI 1 IN D EX • • • • • • Q U IC K R E F E R E N C E G U ID E TO H IT A C H I IC M EM O R IES . 8 MOS R A M .

Contextual Info: Preliminary HM10474-8,HM10474-10 1 0 2 4 - w ord x 4 -b it Fully D e cod e d R and om A c c e s s M em ory The H M 10474 is E C L 10k compatible, 1024-words x 4-bit, read write, random access memory developed for high speed systems such as scratch pads and control/buffer storages.

Contextual Info: H M 100470 4 0 9 6 - word x 1-b it Fully Decoded Random A ccess Memory The HM100470 is a 4096-words x 1-bit, read/write, random access memory developed for high speed systems such as scratch pads and control buffer storages. The fabrication process is the Hitachi's low capacitance, oxide

D1323

Abstract: 100484
Contextual Info: HM100484-10 Preliminary 4096-wrod x 4-bit Fully Decoded Random Access Memory The H M 100484 is E C L 100k compatible, 4096-words by 4-bits read/write random access memory developed for high speed systems such as acratch pads and control/buffer storage. Features

wv1 transistor

Abstract: KTD2058 KTB1366
Contextual Info: KOREA ELECTRONICS CO.,LTD. SEMICONDUCTOR TECHNICAL DATA KTB1366 TRIPLE DIFFUSED PNP TRANSISTOR GENERAL PURPOSE APPLICATION. FEATURES • Low Collector Saturation Voltage : VcE sat =-1 .OV(Max.) at IC=-2A, IB=-0.2A. • Collector Power Dissipation : PC=25W (Tc=25°C)

Contextual Info: DATASHEET APRIL 1997 Revision 2.0 LXT915 Simple Quad Ethernet Repeater The LXT915 is an integrated multi-port repeater designed for mixed-media networks. It provides all the active cir­ Four integrated 10BASE-T transceivers and one AUI transceiver on a single chip

613H

Contextual Info: SN75160B OCTAL GENERAL PURPOSE INTERFACE BUS TRANSCEIVER D 2 5 2 5 , O CTOBER 1 9 8 5 MEETS IEEE STA N D A R D 4 8 8 -1 9 7 8 GPIB 8-Channel Bidirectional Transceiver DW. J. OR N PACKAGE (TOP VIEW) Power-Up/Power-Down Protection (Glitch-Free) L J TEC r •

Contextual Info: HM10480,HM10480F 16,384-w ords x 1-bit Fully Decoded Random Access Mem ory The H M 1 0 4 8 0 is EC L 10K com patible, 16,384-words x 1-bit, read/w rite random access memory developed fo r high speed HM 104S0 systems such as scratch pads and co n tro l/b u ffer storages.

Contextual Info: MITSUBISHI ICs AV COMMON M52688P/FP 8-BIT A-D CONVERTER FOR VIDEO EQUIPMENT DESCRIPTION The M52688P/FP is a semiconductor integrated circuit designed as 8-bit high-speed A-D converter. The type employed is all-parallel type (flash type) that achieves a high conversion

asterm

Contextual Info: DS2407 m a i i æ l ^ D S 2 4 0 7 Dual Addressable Switch Plus • h a c o w u c t o t K _ B it M e m o r y ii FEATURES PIN ASSIGNMENT • Open drain PIO p in s are controlled and their logic level can be determined over 1—WireT^ bus for d o s e d -io o p control

sg4a

Abstract: M52694P xtal 3.57MHz SG1A sg10c m52694 IRL19 SG-10A SG-10B
Contextual Info: MITSUBISHI ICs AV COMMON M52694P BURST LOCK CLOCK GENERATOR DESCRIPTION PIN CONFIGURATION The M52694P is a semiconductor integrated circuit develop­ ed for analog signal processing in the picture-in-picture S UB V ID EO IN system. GND This 1C contains a burst-lock clock generating circuit, analog

mrah

Contextual Info: VITELIC V V51C256L FAMILY HIGH PERFORMANCE LOW POWER 256/Cx 1 BIT CMOS DYNAMIC RAM V51C256L-12 V51C256L-15 V51C256L-20 Maximum Access Time ns 120 150 200 Maximum Column Address Access Time (ns) 60 70 90 Maximum C M O S Standby Current (mA) 0.1 0.1 0.1 power. All inputs and outputs are TTL compatible.

Contextual Info: VITELIC M r VITELIC Y CORP 03 D E ^502310 0000153 7 | . T - M b —*2.3 - t5 VS1C256L FAMILY HIGH PERFORMANCE LOW POWER 256K X 1 BIT CMOS DYNAMIC RAM V51C256L-12 V51C256L-15 V51C256L-20 Maximum Access Time ns) Maximum Column Address Access Time (ns) 120

8-port lan hub schematic

Abstract: XT914 nd4nc 5cte LXT914
Contextual Info: DATA S H E E T JUNE 1997 LXT914 Revision 2.2 Flexible Quad Ethernet Repeater The LXT914 is an integrated multi-port repeater designed for mixed-media networks. It provides all the active cir­ cuitry required for the repeater function in a single CMOS device. It includes one Attachment Unit Interface AUI

12B36

Abstract: RBS 2102 48022 B918 SEQ100 aeq68 MC141532 MC141532T MC141533 MCC141532Z
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA LCD Segment / Common Driver with Controller MC141532 MC141533 CMOS MC141532 / MC141533 is a CMOS LCD Driver which consists of 4 an­ nunciator outputs and 153 high voltage LCD driving signals 33 commons and 120 segments . MC141532 is one sided common output while MC141533 is

mecl mttl

Abstract: motorola 12514 divide-by-10 mttl
Contextual Info: M M O T O R O L A Military 12513 Two Modulus Prescaler ELECTRICALLY TESTED PER: MPG 12513 The 12513 is a two-modulus prescaler which will divide by 10 and 11. A MECLto-MTTL translator is provided to interface with the 12514 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source.