UPSETS Search Results

CDFP4-F16

Abstract: HCTS193DMSR HCTS193HMSR HCTS193KMSR HCTS193MS
Contextual Info: HCTS193MS Radiation Hardened Synchronous 4-Bit Up/Down Counter September 1995 Features • • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ)

2012 ics class X date sheet

Abstract: HCS32D HCS32DMSR HCS32HMSR HCS32K HCS32KMSR HCS32MS
Contextual Info: HCS32MS Radiation Hardened Quad 2-Input OR Gate September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCS109MS

Abstract: CDFP4-F16 HCS109DMSR HCS109HMSR HCS109KMSR HCS109
Contextual Info: HCS109MS Radiation Hardened Dual JK Flip Flop September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCS00HMSR

Abstract: HCS00D HCS00DMSR HCS00K HCS00KMSR HCS00MS
Contextual Info: HCS00MS Radiation Hardened Quad 2-Input NAND Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCS273KMSR

Abstract: HCS273 HCS273DMSR HCS273HMSR HCS273MS
Contextual Info: HCS273MS Radiation Hardened Octal D Flip-Flop September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS20D

Abstract: HCTS20DMSR HCTS20HMSR HCTS20K HCTS20KMSR HCTS20MS
Contextual Info: HCTS20MS TM Radiation Hardened Dual 4-Input NAND Gate September 1995 Features • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day

CDFP4-F16

Abstract: HCTS161ADMSR HCTS161AHMSR HCTS161AKMSR HCTS161AMS
Contextual Info: HCTS161AMS Radiation Hardened Synchronous Counter September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • Minimum LET for SEU Upsets: >100 MEV-cm2/mg

HCTS30

Abstract: HCTS30DMSR HCTS30HMSR HCTS30KMSR HCTS30MS
Contextual Info: HCTS30MS Radiation Hardened 8-Input NAND Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS574DMSR

Abstract: HCTS574HMSR HCTS574KMSR HCTS574MS
Contextual Info: HCTS574MS August 1995 Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered Features • • • • • • • • • • • • • Pinouts 3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD Si SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS02D

Abstract: HCTS02DMSR HCTS02HMSR HCTS02K HCTS02KMSR HCTS02MS
Contextual Info: HCTS02MS Radiation Hardened Quad 2-Input NOR Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD(Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

Contextual Info: HCTS163MS 3 Radiation Hardened Synchronous Counter September 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP) M IL-STD-1835 CDIP2-T16 TOP VIEW > Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS7266DMSR

Abstract: HCTS7266HMSR HCTS7266KMSR HCTS7266MS
Contextual Info: HCTS7266MS Radiation Hardened Quad 2-Input Exclusive NOR Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

vickers servo

Abstract: vickers servo drive Allen-bradley servo motor linear displacement transducer Balluff btl hydraulic analog servo controller MOOG valves temposonic 1771-QB moog
Contextual Info: Product Data Linear Positioning Module Cat. No. 1771ĆQB Benefits Fast system control – Fast update times on the 1771 -QB module (2 ms for servo loop and digital measurement updates) give you fast response to position command and load upsets. Accurate system control – The resolution over 60 inches has improved to

CDFP3-F14

Abstract: HCTS4002D HCTS4002DMSR HCTS4002HMSR HCTS4002K HCTS4002KMSR HCTS4002MS
Contextual Info: HCTS4002MS Radiation Hardened Dual 4-Input NOR Gate August 1995 Features Pinouts • 3 Micron Radiation Hardened CMOS SOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

LGA 478 SOCKET PIN LAYOUT

Abstract: RTAX2000
Contextual Info: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

Contextual Info: v2 . 1 RTSX-S RadTolerant FPGAs Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTAX2000

Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

RTAX2000

Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Contextual Info: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

CDFP4-F16

Abstract: HCTS147DMSR HCTS147HMSR HCTS147KMSR HCTS147MS
Contextual Info: HCTS147MS Radiation Hardened 10-to-4 Line Priority Encoder September 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS132D

Abstract: HCTS132DMSR HCTS132HMSR HCTS132K HCTS132KMSR HCTS132MS
Contextual Info: HCTS132MS TM Radiation Hardened Quad 2-Input NAND Schmitt Trigger August 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T14 TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

HCTS21MS

Abstract: HCTS21D HCTS21DMSR HCTS21HMSR HCTS21K HCTS21KMSR
Contextual Info: HCTS21MS Radiation Hardened Dual 4-Input AND Gate October 1995 Features Pinouts • 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-183S CDIP2-T14, LEAD FINISH C TOP VIEW • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg

56 pin edac connector

Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
Contextual Info: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case

RTSX32su

Abstract: Actel a54sx72a tid Silicon Sculptor II
Contextual Info: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case