UPD48 Search Results

Contextual Info: UPD482445G5-60 1/2 IL08D C-MOS 4M-BIT DUALPORT GRAPHICS BUFFER —TOP VIEW— 30 1 VDD DT/OE IN 2 3 GND 70 SC 69 SE IN 31 IN 32 33 GND 68 34 SIO0 I/O 4 67 SIO15 W0/IO0 I/O 5 66 W15/IO15 SIO1 W1/IO1 I/O I/O 6 7 8 VDD I/O 65 SIO14 39 64 W14/IO14 40 I/O W15/IO15

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT UPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The ,uPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits x 2 banks

Contextual Info: NEC NEC Electronics Inc. JLIPD482444, 482445 4M Video RAM Preliminary Information_ Description The ¿/PD482444 fast-page and /UPD482445 hyper-page video RAMs have a random access p o rt and a serial read/write port. The serial read/write p o rt is connected

UPD482445GW-70

Abstract: UPD482445
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT UPD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT D es crip tio n The ,uPD482444 and ,uPD482445 have a random access port and a serial access port. The random access port has a 4M-bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT LINE BUFFER 5K-WORD BY 8-BIT Description The ^P D 485505 is a 5,048 w ords by 8 bits high speed FIFO First In First Out line buffer. Its CMOS static circuitry provides high speed access and low power consum ption. The ,uPD485505 can be used fo r one line delay and tim e axis conversion in high speed facsim ile machines and

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT UPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The ,uPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits x 2 banks random access port.

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT UPD4811650 for Rev.E 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The ,uPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits x 2 banks

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT ^ 0 4 8 1 8 5 0 for Rev.L 8 M-BIT SYNCHRONOUS GRAM 128K-WORD BY 32-BIT BY 2-BANK Description The ,uPD481850 is a synchronous graphics memory SGRAM organized as 131,072 words x 32 bits x 2 banks random access port.

Contextual Info: UPD485505G-25 IL00 C-MOS 40 K 5,048 x 8 -BIT FIFO MEMORY —TOP VIEW— 24 24 DI 0 IN DO 0 OUT 1 23 22 DO 1 OUT 2 23 DI 1 IN DO 2 OUT 3 22 DI 2 IN 21 16 15 14 DO 3 OUT 4 RE IN 5 21 DI 3 IN 13 WE IN 8 20 17 RSTR IN 6 19 RSTW IN 19 7 GND RCK IN 8 VDD 18 6 DI 0

en2 n5 nec

Contextual Info: AUG l i 1992 SEC NEC Electronics Inc. fiPD485505 Line Buffer for Communications Systems Preliminary Information August 1992 Description Pin Configurations The /UPD485505 is a 5048-word by 8-bit dual-port line buffer fabricated with a silicon-gate CMOS process.

nec dsp 32bit opcode

Abstract: D481850
Contextual Info: PRELIMINARY NEC / MOS Integrated Circuit UPD481850 8Mb Synchronous Graphics Memory 128Kword x 32b it x 2 Banks p.PD481850 is a synchronous graphics memory (SGRAM) organized as 128Kwords x 32bit x 2 Bank random access port. This device can operate up to 100MHz by using synchronous

Contextual Info: UPD482445LGW 1/3 IL22 C-MOS 4M-BIT DUAL PORT GRAPHICS BUFFER —TOP VIEW— 1 VDD DT/OE IN 2 3 GND SIO0 I/O 4 W0/IO0 I/O 5 SIO1 I/O 6 W1/IO1 I/O 7 8 VDD SIO2 I/O 9 W2/IO2 I/O 10 SIO3 I/O 11 W3/IO3 I/O 12 13 GND SIO4 I/O 14 W4/IO4 I/O 15 SIO5 I/O 16 W5/IO5 I/O 17

A5048

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT UPD485505 LINE BUFFER 5 K-W ORD BY 8-BIT Description The /¿PD485505 is a 5,048 words by 8 bits high speed FIFO First In First Out line buffer. Its CMOS static circuitry provides high speed access and low power consumption.

Contextual Info: P R E LIM IN A R Y DA TA SH EE T MOS INTEGRATED CIRCUIT aîPD4811650 for Rev.K 16 M-BIT SYNCHRONOUS GRAM 256K-WORD BY 32-BIT BY 2-BANK Description The ,uPD4811650 is a synchronous graphics memory SGRAM organized as 262,144 words x 32 bits x 2 banks random access port.

jUPD482234

Abstract: D482234 482234LE UPD482235
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ¿¿PD482234, 482235 2M-Bit Dual Port Graphics Buffer 256K-WORD BY 8-BIT Description The ,uPD482234 and ^P D 482235 have a random access port and a serial access port. The random access port h a s a 2 M -b it 2 6 2 ,144 w ords x 8 bits mem ory cell array structure. The serial access port can perform clock operations

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD48288209, 48288218, 48288236 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209 is a 33,554,432-word by 9 bit, the μPD48288218 is a 16,777,216 word by 18 bit and the μPD48288236 is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT LINE BUFFER 5 K-WORD BY 16-BIT/10K-W ORD BY 8-BIT Description The /¿PD485506 is a high speed FIFO First In First Out line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits.

Rambus RDRAM ASIC

Abstract: RDRAM cross reference NEC RDRAM 36 REF05
Contextual Info: PRELIMINARY UATA SHEET NEC MOS INTEGRATED CIRCUIT 16M-BIT Rambus DRAM 1M-WORD X 8-BIT X 2-BANK Description The 16-Megabit Rambus DRAM RDRAM™ is an extremely-high-speed CMOS DRAM organized as 2M words by 8 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus Signaling

NL1031

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT /¿ P D 4 8 8 3 0 L 8M-BIT Rambus DRAM 1M-WORD X 8-BIT X 1-BANK Description The 8-Megabit Ram bus DRAM RD R A M ™ is an extremely-high-speed C M O S DRAM organized as 1M w ords by 8 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Ram bus Signaling

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT ¿¿PD488448, 488488 128/144 M-bit Direct Rambus DRAM Description The Direct Rambus DRAM Direct RDRAM™ is a general purpose high-performance memory device suitable for use in a broad range of applications including com puter memory, graphics, video, and any other application where

Contextual Info: JJPD485506 Line Buffer for Communications Systems NEC Electronics Inc. Description Pin Configurations The /j PD485506 is a 5048-w ord by 16-bit d ual-port line buffer fab ric a te d w ith a silicon-gate CM OS process. T he device is capab le of asynchronous read and w rite

Nec concurrent rdram

Abstract: concurrent rdram NEC concurrent rdram CI 7424
Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT |xPD488170 18M bit Rambus DRAM 1 Mword x 9bit x 2bank Description |J The 18-Megabit Rambus DRAM (RDRAM™) Is an extremely-high-speed CMOS DRAM organized a sJM w o r llb y 9 bits and capable of bursting up to 256 bytes of data at 2 ns per byte. The use of Rambus S igrgling L o 1 |l% |S L )

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT /¿PD488170L 18M-BIT Rambus DRAM 1M-WORD X 9-BIT X 2-BANK Description The 18-Megabit Rambus DRAM RDRAM™ is an extrem ely-high-speed CMOS DRAM organized as 2M w o rds by 9 bits and capable o f bursting up to 256 bytes of data at 2 ns per byte. The use o f Rambus S ignaling

mip 2h2

Abstract: Solid state CCIR ca 152 sh ei 33ca RGB565 to rgb888 PMB 8888 660-227 331 dim hee nv tag 8514 SERVICE MANUAL tv sharp A205D
Contextual Info: Advance This document contains information on a product under development. Information is not warranted and is subject to change. Bt2166 High-Performance PCI/AGP 3D Video/Graphics Controller Applications Feature Summary • • • • • • • Microsoft Windows 95 Direct3D accelerator