UG69 Search Results

CEI11

Abstract: PRBS11 UG371 XC6VHX255T-FF1155 FPGA Virtex 6 Ethernet h8440 PRBS31 DSP48E1 FF1155 FF1923
Contextual Info: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.0 February 16, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or

Contextual Info: Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC ADF7024 Data Sheet FEATURES Receiver performance Highly linear: −11.5 dBm input IP3 Blocking: 76 dB at 10 MHz offset Receiver sensitivity, bit error rate BER −111 dBm at 9.6 kbps −105 dBm at 100 kbps

10Gbase-kr backplane connector

Abstract: Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr
Contextual Info: LogiCORE IP 10-Gigabit Ethernet PCS/PMA v2.3 DS739 April 24, 2012 Product Specification Introduction The LogiCORE IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment PCS/PMA core forms a seamless interface between the Xilinx 10-Gigabit Ethernet Media Access

MDIO clause 45 specification

Abstract: xaui marvell "reduced xaui" dune Marvell PHY Xilinx virtex rxaui marvell XGXS Marvell design guide marvell ethernet PHY transceivers Marvell PHY register map DS740
Contextual Info: LogiCORE IP RXAUI v2.3 DS740 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP RXAUI core is a high-performance, low pin count 10 Gb/s interface intended to allow physical separation between the data-link layer and

XC6SLX150T-FGG676

Abstract: xc6slx150t-fgg676-3 XC6SLX150T_FGG676 usb 2.0 implementation using verilog verilog code for uart apb video pattern generator "displayport receiver" xc6slx150t displayport 1.2 SPARTAN-6 GTP
Contextual Info: Application Note: Spartan-6 FPGAs Implementing a DisplayPort Source Policy Maker Using a MicroBlaze Embedded Processor XAPP493 v1.0 July 21, 2010 Summary Author: Tom Strader and Matt Ouellette This application note describes the implementation of a DisplayPort Source Policy Maker

M39012/26-0101

Abstract: M39012/01-0005 UG-709 UG-1213/U ug-1412/u UG-573 UG-931/U UG 1412 U M39012/26-0011 UG-447/U
Contextual Info: MIL-PRF-39012 QPL Connectors MIL-PRF-55339 QPL Adapters Online Catalog Volume 1 Delta QPL connectors and adapters meet or exceed all requirements of MIL-PRF-39012 and MIL-PRF-55339. Because these specifications change periodically, please visit DSCC’s website at

ADM7154

Contextual Info: User Guide UG-696 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADM7154 and ADM7155 Linear Regulators

FO-10GGBLCX20-001

Abstract: DX58SO asus rampage
Contextual Info: Kintex-7 FPGA Connectivity Kit Getting Started Guide UG929 v1.0 June 26, 2012 XPM0402915-01 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

UG69

Contextual Info: AN-1315 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Autonomous IR Calibration on the ADF7024 by Liam O’Hora and Conor O’Mahony INTRODUCTION Heterodyne radios, such as the ADF7024 transceiver, use a

64b/66b encoder

Abstract: PRBS31 transistor B1010 DSP48E1 FF1155 FF1923 FF1924 UG371 XC6VLX760 transistor b1011
Contextual Info: Virtex-6 FPGA GTH Transceivers User Guide UG371 v2.1 October 4, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or

Contextual Info: Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC ADF7024 Data Sheet FEATURES Receiver performance Highly linear: −11.5 dBm input IP3 Blocking: 76 dB at 10 MHz offset Receiver sensitivity, bit error rate BER −111 dBm at 9.6 kbps −105 dBm at 100 kbps