TTL19 Search Results

diode s1 77

Abstract: S124 diode s1 diode s1 74 socket s1 S1-100 S1-128
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-118 S1-110 S1-103 S1-100 TTL1 TTL8 C3 B4 TTL11 C4 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 TTL20 C12 TTL21 C13 TTL22 C14 TTL23 C15 TTL24 C16 TTL25 C17 PVCC C18 TTL26 C19 PVPP C20 TTL28

S124

Abstract: diode s1 74 s167 TTL-45 HW-133 S176
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 A5 D3 D2 D1 D0 S1-36 S1-33 S1-32 S1-31 TTL1 TTL4 B2 C3 C4 TTL12 B5 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 PVCC B7 A8 +5V B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7

Socket S1g3

Abstract: A7 B14 B12 diode S1-N13 Socket S1g2 S1G15 TTL-45 HW-133 S1-F13 S1G3
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 A5 D3 D2 D1 D0 S1-M15 S1-N14 S1-P14 S1-N12 TTL1 TTL4 B2 C3 C4 TTL12 B5 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11

S124

Abstract: S1-11 socket s1 S1-50
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-55 S1-52 S1-50 S1-49 TTL1 P1 D4 B1 S1-56 S1-60 D6 TTL2 C1 TTL5 C2 TTL4 B2 TTL7 B3 TTL8 C3 TTL10 B4 TTL11 C4 TTL13 C5 TTL15 C6 TTL16 C7 TTL17 C8 TTL19 C9 AGND C10 PVCC C11 TTL20 C12 TTL21 C13 TDI S1-45 S1-48

CS 5211

Abstract: XC1704 U2A18 A1529 ALI M16 ID99 b21 a03 aO d07 S234 TTL-45
Contextual Info: A [00:1B] P1 P1 P1 S1-37 AOO TTLO A1 TTL3 A2 51-5 TMS 52-11 CEO TTL1 B1 DV TTL4 B2 D05 D02 51-21 TTL7 B3 5 2- 27 TTL10 B4 A5 51-40 TTL12 B5 AID5 A6 52-2 T T L14 B6 AID4 A7 PVCC B7 AIDO A8 +5V B8 TTL6 A3 TTL9 A4 AID6 AID1 DATA DO See note 5. A9 A 10 AID3 A ll

MI b11

Abstract: A241 ISA-96 TTL-45
Contextual Info: TTLO TTL3 T TL6 T TL9 AID6 P1 P1 P1 DATA2 A1 DATAI A2 CEO A3 DATAD A4 S I —6 TTL1 S I —16 TTL4 51—13 TTL7 51-1 TTL10 A5 TTL12 TTL2 C1 DATA4 S I —14- TTL5 C2 DATA6 B3 TTL8 C3 B4 TTL11 C4 B2 A6 TTL14 B6 AID4 A7 PVCC B7 AIDO A8 +5V B8 AID1 A9 TTL18 B9

Contextual Info: Cow profite > 1 C ^ t 2l CO M PATIBLE A lAP* PIXEL CLOCK GENERATOR MODULE j # T^L FAST input and output # Output wavetrain can be synchronized with random events # 20-pin DIP package .290 high # Available in frequencies from 2MHz to 30MHz # Output frequencies controlled to within ±2%

asynchronous fifo vhdl

Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
Contextual Info: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com

SSFXLDM-TTL-50G

Abstract: SSFXLDM-TTL-90T
Contextual Info: ta□ E D ENGINEERED • 3333203 Q0Q07ÛS TL3 EGC COMPONENTS C C O M P A T IB L E -TAP O G IC MODULE T2L input and outputs Delays stable and precise 14-pin Space Saver package Leads - thru-hole, J, Gull Wing or Tucked # Available in delays from 15 to 1000ns

Socket S1g1

Abstract: HW-133 XC95144XL S1A13 TTL32 s1d1 TTL-45 s1n6 S1-N13
Contextual Info: A1 D3 TTL3 A2 _D2_ T TL6 A3 T TL9 A4 TTLO AID6 AID5 51—A 1 P1 P1 TTL1 S1-M 13 TTL4 51—NI Z TTL7 S1-H11 TTL10 GND TTL12 A6 TTL14 B1 B6 TCK VCC A8 +5V B8 AID1 A9 TTL18 B9 AID7 A ll TTL44 A 12 AGND A 13 CGND A14 AGND MOUNTI NG HOLES B12 B16 S1-E11 B17 AGND

si111

Abstract: SI-111 S1-V11 S1L-10 HW-133 Socket S1g4 S1B14 TTL-45
Contextual Info: P1 TTLO TTL3 TTL6 TTL9 AID6 AID5 AID4 AIDO AID1 AID2 AID3 AID7 AGND CGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND PVPP P1 A1 A2 A3 A4 A5 A6 A7 A8 A9 _ Q i_ S 1 -P 2 0 J22_ S 1 -V 2 0 D1 S 1 -Y 2 0 J2Ù _ S 1 -Y 1 9

diode t25 4 B9

Abstract: transistor af18 socket s1 diode t25 4 d9
Contextual Info: P1 TTL0 D3 A1 TTL3 A2 TTL6 A3 TTL9 P1 D2 D1 D0 A4 S1-W2 S1-AA4 S1-AD3 S1-AE3 TTL1 P1 D4 B1 TTL4 B2 TTL7 B3 TTL10 B4 AID6 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 +5V B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 S1-U2 S1-R2 D6 TDI TTL2

HW-133-PC68

Abstract: HW-133 S124 socket s1 S1-25 s159 socket s1 a1 a2 61S161 XC7354 MRX TTL-45
Contextual Info: ZONE REV 01 P1 TTL0 TTL3 A2 TTL6 A3 TTL9 A4 AID6 AID5 D3/D0 D2/D4 S1-25 S1-29 S1-28 S1-27 TTL1 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 A6 TTL14 B6 D1/D3 D0/D2 AID4 A7 PVCC B7 AID0 A8 +5V B8 A9 AID2 AID3 TTL18 B9 A10 AGND B10 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13

S124

Abstract: diode s1 85
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-57 S1-54 S1-52 S1-51 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

socket s1

Abstract: diode s1 61 diode s1 77 diode s1 85 S124 040 d10 diode s1 diode s1 74 HW-133-PQ160 S1 18
Contextual Info: P1 TTL0 P1 D3 A1 TTL3 A2 TTL6 A3 TTL9 A4 D2 D1 D0 S1-90 S1-82 S1-79 S1-77 TTL1 TTL4 B2 TTL7 B3 TTL10 B4 A5 TTL12 B5 AID5 A6 TTL14 B6 AID4 A7 PVCC B7 AID0 A8 PVSP B8 AID1 A9 TTL18 B9 AID2 A10 AGND B10 AID3 A11 TTL44 B11 AID7 A12 AGND B12 AGND A13 AGND B13 CGND

diode b27

Abstract: diode b26 TTL20 S124 diode b29 socket s1 53 S1 TTL-45
Contextual Info: ZONE REV 01 DATE REVISION DESCRIPTION INITIAL RELEASE PER DCN #6875 DRAWN 5/23/95 CHECK EWR APPVD CH FE Further Revision history is available on Matrix. P1 TTL0 A1 TTL3 A2 TTL6 A3 TTL9 A4 AID6 P1 D3 D2 D1 S1-7 S1-8 S1-9 S1-10 TTL1 P1 D4 B1 TTL4 B2 S1-63 S1-61

full subtractor circuit using xor and nand gates

Abstract: 74138 full subtractor 3-input-XOR 74138 decoder 7474 D flip-flop vhdl code for 8-bit BCD adder data sheet 74139 vhdl code for 8 bit ODD parity generator 74171 74594
Contextual Info: Chapter 10 - Macro Library Reference Chapter 10: The Macro Library The QuickLogic Macro Library contains over 475 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy

synchronous inverter schematic ims 1600

Abstract: elcot tv kit circuit diagram iosq 050 pin diagram for IC cd 1619 cp in fm smd code transistor sd IL44 Z ET 439 IL44 transistor ksv3100a UTM ceramic RESISTOR 390 210-9
Contextual Info: CONFIGURABLE DESIGN PLD 1 S i 2 0 Regan Brampton, Tel: (4 1 6 Fax: (4 1 6 ) 9 • Si APPLICATION BOOK F P GA 9 LOGIC 4 Ì 4(I M A S S O C IA T E S Road, Unit 14 O ntario L 7 A 1C3 8 4 0 -6 0 6 6 8 4 0 -6 0 9 1 • GATE A R R A Y 1 9 9 5 iilmËL Atmel Programmable Logic Devices (PLDs)

XC95108XL

Abstract: si122 ISA-96 HW-133 RH A4 130 XC95144XL IS9B TTL-45 SI-122
Contextual Info: P1 P1 TTLO TTL3 TTL6 TTL9 AID6 AID5 _Q3_ A1 A2 A3 A4 5 1-B O _Q2_ 5 1 -7 4 DI 5 1 -7 1 _BD_ S I— 69 TT L1 TTL4 TTL7 TTL10 GND A5 TTL12 A6 TTL14 P1 5 1 -8 2 TTL2 5 1 -8 7 TTL5 C2 B3 TTL8 C3 B4 TTL11 C4 B7 AI DO A8 +5V B8 AID1 A9 TTL18 B9 AID3 AID7 All TTL44

9536XL

Abstract: HW-133 HW-133-VQ64 A2 5160 64-pin VQFP xc9572xl TTL-45 ISA-96
Contextual Info: A1 D3ÍA11 A2 D2 A1D) A3 Dlf A9Ì TTL9 A4 DO(AB) AID6 A5 TTLO TTL3 TTL6 P1 P1 P1 S I—24S1-22 GND B2 D6(D1) S1-35 TTL5 C2 B3 TTL8 C3 TTL10 B4 TTL11 C4 TTL12 B5 TTL13 C5 TTL15 C6 TTL16 C7 T TL7 S I—19 D4ÍA12) TTL2 T T L4 S1-20 B1 S1-25 TTL1 AID5 A6 TTL14

Contextual Info: tozo profile t 2l COMPATIBLE SIP LOGIC DELAY UNE M ìn ì > # Available in delays from 5 to 500ns T h e M S F L D L -T T L is offered in 4 8 delays from 5ns to 500ns. Delay tolerances are m aintained as shown in the accompanying part num ber table, w hen tested under the "Test Conditions” shown. Delay

ttl74

Abstract: TTL138 TTL74 series 2-input OR gate 7400 family TTL373 TTL06 TTL244 ttl273 QL16X24 marking code JRW
Contextual Info: tu« i 1WI pASIC m 1 FAMILY V iaL ink T echnology V ery H igh S peed CMOS FPGAs PRELIMINARY DA TA FAMILY HIGHLIGHTS M ay 1991 Very High Speed - ViaLink™ Metal-to-metal programmable-via antifuse technology, ensures count«' speeds over 100 MHz, and logic

7474 D flip-flop

Abstract: vhdl code for 74154 4-to-16 decoder 7478 J-K Flip-Flop vhdl code for 74194 74138 full subtractor 3-8 decoder 74138 shift register by using D flip-flop 7474 full subtractor circuit using xor and nand gates vhdl code for 8-bit BCD adder 74823 FULL ADDER
Contextual Info: Chapter 3 - Macro Library Reference Chapter 3: The Macro Library The QuickLogic Macro Library contains over 500 macros and macro building blocks. While these macros offer a wide range of functions and flexibility, they fall into familiar functional groups. The naming conventions employed in the library are easy

Contextual Info: lozu profite t 2l COMPATIBLE 10-TAP tO G IC DELAY MODULE # T2L input and outputs # Delays stable and precise # 14-pin DIP package time is measured at the +1.5V level on the leading edge. Rise time for all modules is 4ns maximum when measured from 0.8V to 2.0V. Temperature coefficient of delay is approxi­