TTL IC PARAMETER Search Results

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

ic 3525 internal block diagram

Abstract: ic 3525
Contextual Info: SYNERGY SINGLE SUPPLY OCTAL PECL/TTL-tO -TTL C'° SY100H646 S E M IC O N D U C T O R FEATURES PECL/TTL-to-TTL version of popular ECLinPS El 11 Meets specifications required to drive highperformance x86 processors Guaranteed low skew specification Three-state enable

FT232R

Abstract: FT232RQ TTL232R-3V3 ft232r MAX232 MAX232 TTL232R TTL-232R TTL-232R-3V3 UART TTL buffer serial port to ttl using max232
Contextual Info: Future Technology Devices International Ltd. TTL-232R USB to TTL Serial Converter Cable The TTL-232R is a USB to TTL serial converter cable incorporating FTDI’s FT232RQ USB - Serial UART interface IC device, the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. It is designed

max232 rts cts

Abstract: TTL-232R-3V3 cmos 3v3 TTL232R-3V3 FT232RQ FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232
Contextual Info: Future Technology Devices International Ltd. TTL-232R-3V3 USB to TTL Serial Converter Cable The TTL-232R-3V3 is a USB to TTL serial converter cable incorporating FTDI’s FT232RQ USB - Serial UART interface IC device, the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. It

Contextual Info: MBM93419 FUJITSU M IC R O E L E C T R O N IC S . INC. TTL 576-BIT BIPOLAR RANDOM ACCESS MEMORY DESCRIPTION The Fujitsu MBM93419 is a high speed TTL read/write randomaccess memory, organized as 64 words by 9 bits, with opencollector outputs. M BM93419 is packaged in a

Contextual Info: « 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE SYNERGY SY10H600 SY100H600 S E M IC O N D U C T O R FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise

eel -16-2005

Abstract: SY100H842 SY100H842ZC SY10H842 SY10H842ZC
Contextual Info: * SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY SEM IC O N D U C TO R FEATURES • ■ ■ ■ C lockw orks SY10H842 SY100H842 DESCRIPTION Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec Differential Internal design for Increased noise

Contextual Info: * 9-BIT LATCHED ECL-TO -TTL SYNERGY SY10H603 SY100H603 S E M IC O N D U C T O R FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply

16f8

Contextual Info: data detayW devices;inc. 7a s t L o g ic Programmable Delay Units SERIES: PDU-16F 6-Bit TTL Interfaced Features: T es t C o nditions: • Input & Output TTL buffered ■ 6-Bit TTL program m able delay line ■ Two (2) Separate outputs; inverting and non-inverting.

SY100S811

Abstract: SY100S811JC SY100S811JCTR SY100S811ZC SY100S811ZCTR
Contextual Info: * SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec V bb output TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design

F100K

Abstract: SY100S391 diode d4c Vcc-1035
Contextual Info: * LOW-POWER HEX TTL-TO-PECL TRANSLATOR SYNERGY SY100S391 S E M IC O N D U C T O R DESCRIPTION FEATURES The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this

Contextual Info: *SYNERGY SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE S E M IC O N D U C T O R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: O SING LE SUPPLY PEC L-TTL 1:4 C LO C K DRIVER SYNERGY S E M IC O N D U C T O R FEATURES S Y ^o'lo'ohS l DESCRIPTION • Translates positive ECL to TTL PECL-TTL The SY10H841 and SY100H841 are single supply, low skew translating 1:4 clock drivers. The devices feature a 24m A TTL output stage, with AC

SN74ALS900

Abstract: Advanced Schottky Family ci 741 SN54ALS900 LS 741
Contextual Info: Attachment B-15 y PRELIMINARY DATA SHEET ADVANCED LOW-POWER SCHOTTKY TTL TYPES SN54ALS900 and SN74ALS900 QUAD 2 - INPUT NAND BUFFERS QUAD 2- INPUT NAND BUFFERS * * * ELECTRICAL PINOUT ADVANCED OX IDE-ISOLATED, IONIMPLANTED SCHOTTKY TTL PROCESS pos itive 1og ic :

SY100H841

Abstract: SY10H841 SY10H841ZC
Contextual Info: * SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE SYNERGY S E M IC O N D U C T O R Clockworks SY10H841 SY100H841 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

100HF646

Abstract: ATT10 H600 H646 0D023
Contextual Info: SING LE SUPPLY OCTAL SYNERGY Clockworks P EC L/TTL-to-TTL S E M IC O N D U C T O R FEA TU R E S S Y 100 H 646 5 Y1 ° ° H 6 4 6 D ES C R IPTIO N I PECL/TTL-to-TTL version of popular ECLinPS El 11 I Meets specifications required to drive high­ performance x86 processors

F100K

Abstract: SY100S324 SY100S324DC D2418
Contextual Info: * LOW PO W ER HEX TTL-to-E C L TRANSLATO R SYNERGY S E M IC O N D U C T O R FEATURES SY100S324 DESCRIPTION Max. propagation delay of 1,4ns min. of —70mA The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL

Contextual Info: * SINGLE SUPPLY QUAD PECL-TO-TTL WITH O UTPUT ENABLE SYNERGY S E M IC O N D U C T O R Clockworks SY10H841 SY100H841 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

Contextual Info: S E M IC O N D U C T O R tm 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compat­ ible with standard or Schottky TTL. A common Enable E ,

Contextual Info: SINGLE_SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY p rE f LIM m m IN IIIII rv PR AR Y SY1Q 1D0H843 SEM IC O N D U C TO R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for Increased noise

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

Contextual Info: r 3 S t L O g iC Pulse Width Discriminator SERIES: PWD-21 TTL Interfaced data delay \b7 devicesYine. Features: • Auto-insertable. ■ Completely Interfaced with TTL and DTL application. ■ No external components required. ■ P.C. board space economy achieved.

Contextual Info: V SYNERGY Clockworks SY10ELT23 SY100ELT23 DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR S E M IC O N D U C T O R DESCRIPTION FEATURES 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL outputs 24mA TTL outputs Flow-through pinouts

Contextual Info: EFasf Lo g ic 2- Phase data Gated-Delay Line Oscillator del» 14 pins DIP DL0-32F SERIES: TTL Interfaced LCCSf Inc. Features: • ■ ■ ■ ■ ■ ■ ■ Auto-insertable. TTL interfaced. Continuous or keyable wavetrain. Locked syncronization achieved with