TTL IC Search Results

ic 3525 internal block diagram

Abstract: ic 3525
Contextual Info: SYNERGY SINGLE SUPPLY OCTAL PECL/TTL-tO -TTL C'° SY100H646 S E M IC O N D U C T O R FEATURES PECL/TTL-to-TTL version of popular ECLinPS El 11 Meets specifications required to drive highperformance x86 processors Guaranteed low skew specification Three-state enable

max232 rts cts

Abstract: TTL-232R-3V3 cmos 3v3 TTL232R-3V3 FT232RQ FT232R USB UART ttl drive USB CABLE MAX232 for level converter notes on serial communication MAX232
Contextual Info: Future Technology Devices International Ltd. TTL-232R-3V3 USB to TTL Serial Converter Cable The TTL-232R-3V3 is a USB to TTL serial converter cable incorporating FTDI’s FT232RQ USB - Serial UART interface IC device, the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. It

Contextual Info: O SYNERGY SEMICONDUCTOR 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE Guaranteed low skew specification Three-state enable Differential internal design V bb output for single-ended operation Extra TTL and ECL power/ground pins

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

Contextual Info: IDT74GTLP816 GTLP / TTL 1:2 / 1:6 CLOCK DRIVER INDUSTRIAL TEMPERATURE RANGE GTLP/TTL 1:2/1:6 CLOCK DRIVER FEATURES: • • • • • • • • DESCRIPTION: 5V or 3.3V operation Interface between GTLP and TTL logic levels GTLP to TTL 1:6 fanout TTL to GTLP 1:2 fanout

Contextual Info: O SING LE SUPPLY PEC L-TTL 1:4 C LO C K DRIVER SYNERGY S E M IC O N D U C T O R FEATURES S Y ^o'lo'ohS l DESCRIPTION • Translates positive ECL to TTL PECL-TTL The SY10H841 and SY100H841 are single supply, low skew translating 1:4 clock drivers. The devices feature a 24m A TTL output stage, with AC

XEL28

Abstract: marking k8 diode
Contextual Info: 5V TTL-TO-DIFFERENTIAL PECL AND DIFFERENTIAL PECL-TO-TTL TRANSLATOR FEATURES SY10ELT28 SY100ELT28 FINAL DESCRIPTION • Guaranteed AC parameters over temperature: • fMAX > 160MHz TTL • < 5.5ns PECL-to-TTL propagation delay • < 1.5ns tr / tf; PECL output

H600

Abstract: SY100H646L SY10H646L
Contextual Info: 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL Micrel, Inc. Precision Edge SY10H646L ® Precision SY100H646L Edge SY10H646L SY100H646L FEATURES • 3.3V power supply ■ PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE ■ Guaranteed low skew specification

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information TTL to Differential PECL/Differential PECL to TTL Translator MC10ELT28 MC100ELT28 The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL

Contextual Info: Digitally Programmable data delay Delay Units SERIES: PDU-1316 devicesYinc. 4-Bit TTL Interfaced Specifications: Test Conditions: • ■ ■ ■ Input signal requirement: TTL logic Output fan-out: TTL s ch o ttky loads Delay variation: M on o to n ic in one d irection

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

H600

Abstract: SY100H646L SY10H646L SY10H646LJC
Contextual Info: ClockWorks SY10H646L SY100H646L 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL FEATURES DESCRIPTION • 3.3V power supply ■ PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE ■ Guaranteed low skew specification ■ Three-state enable ■ Differential internal design

Contextual Info: ClockWorks SY10H646L SY100H646L FINAL 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL FEATURES DESCRIPTION • 3.3V power supply ■ PECL/TTL-to-TTL version of popular ECLinPS E111AE/LE ■ Guaranteed low skew specification ■ Three-state enable ■ Differential internal design

Contextual Info: « 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE SYNERGY SY10H600 SY100H600 S E M IC O N D U C T O R FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

H600

Abstract: SY100H600 SY10H600 SY10H600JC SY10H600JCTR MECL10KH
Contextual Info: 9-BIT TTL-TO-ECL WITH TTL, ECL ENABLE FEATURES SY10H600 SY100H600 DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs ■ Dual supply

Contextual Info: *SYNERGY SINGLE SUPPLY QUAD PECL-TO-TTL WITH OUTPUT ENABLE S E M IC O N D U C T O R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew ■ Differential internal design for increased noise

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

Contextual Info: SINGLE_SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY p rE f LIM m m IN IIIII rv PR AR Y SY1Q 1D0H843 SEM IC O N D U C TO R DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for Increased noise

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

Contextual Info: A V 3.3V SINGLE SUPPLY QUAD pF r| SYNERGY C lockworks PRELIMINARY SY10H841L SY100H841L T n T T | W |T H PECL-TO-TTL WITH OUTPUT ENABLE S E M IC O N D U C T O R DESCRIPTION FEATURES • 3.3V power supply ■ Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew

Contextual Info: * SINGLE SUPPLY QUAD PECL/TTL-TO-PECL SYNERGY Clockworks SY100S815 SEMICONDUCTOR DESCRIPTION FEATURES Quad PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design

PLCC44 pinout

Abstract: plcc44 pinout numbers 8 shift register by using D flip-flop 74F154 shift register by using D flip-flop 3 bit magnitude comparator octal inverter schmitt trigger non inverting 74f3037 SOT27-1
Contextual Info: Philips Semiconductors Functional Index IC15: FAST TTL LOGIC SERIES Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contextual Info: >0 » SYNERGY 9-BIT LATCHED ECL-TO-TTL SY10H603 SY100H603 SEMICONDUCTOR FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply