TTL 74 Search Results

TTL 7440

Abstract: 9N38 74H40 74S140 74S40 9H40 9N37 9N40 9S40 TTL 7437
Contextual Info: 6006 74H40 9H 40/ 9N 37/ 7437 9N 38/ 7438 9N 40/ 7440 74S40 9S 40/ 74S140 96101 Dual 2-NAND Driver Any TTL Quad 2-NAND Driver Any TTL Any TTL Dual 2-NAND Driver Any TTL Quad 2-NAND Driver Dual 2-NAND Driver Any TTL 96 106 Any TTL Dual 2-NAND Driver 50 0 Driver

AI3D-12

Abstract: AI3D-15 AI3D-20 AI3D-25 AI3D-30 AI3D-35 AI3D-10 AI3D-11
Contextual Info: AI3D Series FAST / TTL Buffered Triple Independent Delays Electrical Specifications at 25OC 14-Pin Package Surface Mount and Thru-hole Versions Delay Tolerance ns FAST/TTL Logic Buffered 14-Pin 74F/TTL Buffered Triple Independent Delays DIP P/N G-SMD P/N

sn75365

Abstract: SN75362 S7001
Contextual Info: FUTURE PRODUCTS AVAILABLE 1ST QTR 74 SN75362 . . . DUAL TTL-TO-MOS DRIVER key features • Dual inverting TTL-to-MOS driver • Versatile interface circuit for use between TTL and high-current, high-voltage systems • Equivalent to 1/2 of SN75365 device but with single input per channel

Contextual Info: « PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP C V M C O rV SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLìnPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification

CY101E383

Abstract: E383 R2170 ecl 84
Contextual Info: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-

7SEG COM ANODE

Abstract: 7-seg 7-seg ANODE COMMON 7seg D143 TTL 74LS48 TTL 7446 decoder 74LS48 7448 decoder decoder 74LS47
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Cont'd 5.5 H — 125 D141 4L.6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I.6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes No Yes

decoder 7448

Abstract: BCD D147 D142 7448 decoder mos 9368 decoder 74LS47 7-seg 9317C ttl 74ls48 9317B
Contextual Info: FAIRCHILD INTERFACE DISPLAY DRIVERS Yes Yes No 1.3 5.5 H — 125 D141 4L,6B, 9B 2 5449 7-Seg Decoder TTL Yes Yes No 9.6 5.5 H — 165 D142 3I 3 54LS/ 74LS49 7-Seg Decoder/ TTL Dvr OC Yes Yes No 1.3 5.5 H — 40 D142 3I,6A, 9A 4 9302 1-of-10 OC Dvr TTL Yes

PDU-1316-20

Abstract: PDU-1316-1 PDU-1316-12 PDU-1316-2 PDU-1316-5 PDU-1316-100 NS225
Contextual Info: data \flaa Digitally Programmable delay \ë SERIES: PDU-1316 De ay Units deviceli«:. 4-Bit TTL Interfaced Specifications: Test Conditions: • Input signal requirement: TTL logic ■ Output fan-out: TTL schottky load ■ Delay variation: Monotonic in one direction

Contextual Info: * SINGLE SUPPLY QUAD PECL/TTL-TO-PECL SYNERGY Clockworks SY100S815 SEMICONDUCTOR DESCRIPTION FEATURES Quad PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design

Contextual Info: INTEGRATED CIRCUITS 74F219A 64-bit TTL bipolar RAM, non-inverting 3-State Product specification IC15 Data Handbook Philips Semiconductors 1996 Jan 05 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) FEATURES 74F219A

DTL or TTL integrated logic circuits

Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450APC

Abstract: 9109 DC fairchild ECL 75450a
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75452ATC

Abstract: 75452A
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

754538

Abstract: 9109 DC 55450B 75450BDC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

55450B

Abstract: 75451B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

74 TTL PACKAGE OUTLINES

Abstract: 75451ATC 1606B 55451A 75451ARC
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75450apc

Abstract: 10125 ecl to ttl fairchild 9112 7S45 pin diagram for all 74 series ttl gates
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0 .0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V - 2 . 0 0.4 90 440 TO-86 6A.9A 9 5 9 5 * Dual ECL-TTL Translator +5.0 - 5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver

75451

Abstract: 55450B 75452B fairchild 9112
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

75452

Abstract: 55450B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 9595* Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

fairchild ECL

Abstract: 75453btc 55450B 754S3B
Contextual Info: INTERFACE SELECTION GUIDE BY DEVICE NUMBER HLDTL-TTL Hex 12 to 20 0.0 0.0 0.4 120 380 TO-86 6A.9A 9112* TTL-HLDTL Hex 12 to 20 0.0 +V -2 .0 0.4 90 440 TO-86 6A.9A 95 9 5 * Dual ECL-TTL Translator +5.0 -5 .2 2.4 0.4 6.0 375 6B TTL-MOS Quad Clock Driver 15 to 21

TTL 7414

Abstract: TTL 7414 data 7414 74LS14 function table 7414 hex not 7414 ttl inverter schmitt trigger 7414 7414 equivalent pin configuration 74LS14 ls14
Contextual Info: 7414, LS14 Signetics Schmitt Triggers Hex Inverter Schmitt Trigger Product Specification Logic Products DESCRIPTION The '14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly

Contextual Info: « 9-BIT TTL-ECL TRANSLATOR SYNERGY SY10H600 SY100H600 SEMICONDUCTOR FEATURES DESCRIPTION • 9-bit ideal for byte-parity applications ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize switching noise ■ ECL and TTL enable inputs

SY100S811

Abstract: SY100S811JC SY100S811JCTR SY100S811ZC SY100S811ZCTR
Contextual Info: SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL FEATURES DESCRIPTION PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec VBB output TTL enable input Selectable TTL or PECL clock input Single +5V supply Differential internal design Similar pin configuration to E111

Contextual Info: IDT74GTLP16612 CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER FEATURES: • • • • • DESCRIPTION: Bidirectional interface between GTLP and TTL logic levels Edge Rate Control Circuit reduces output noise