TTL 154 Search Results

Contextual Info: Signal Processing Digital converters opto coupler transmitters for signal level shifting, isolating and signal regeneration of HTL or TTL signals HEAG 151, 152, 153, 154 Features – Signal level shifting from HTL TTL or TTL HTL – Isolating signal cables to multiple receivers to avoid

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: *SYNERGY PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLinPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification

Contextual Info: « PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP C V M C O rV SEMICONDUCTOR FEATURES Clockworks PRELIMINARY SY10/100H646 DESCRIPTION • PECL/TTL-TTL version of popular ECLìnPS E111 ■ Meets specifications required to drive highperformance x86 processors ■ Guaranteed low skew specification

Contextual Info: M OTOROLA M C 10H 646 M C 100H 646 Product Preview PEC L/TTL-TTL 1:8 C lo ck D istrib u tio n Chip PECL/TTL-TTL 1:8 CLOCK DISTRIBUTION CHIP The MC1 OH/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the Motorola ‘H600 translator series utilize the 28-lead PLCC for

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

Contextual Info: CY10E383 CY101E383 a CYPRESS ~ SEMICONDUCTOR ~ ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional D escription • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpD TTL-to-ECL — 3.5 ns tpD ECL-to-TTL • Low skew < ± 1 ns

5D6 diode

Abstract: Power PQFP 64 10e383 Q809
Contextual Info: CY10E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpj) TTL-to-ECL — 3.5 ns tpj) ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply

Contextual Info: CY10E383 CY101E383 CYPRESS SEMICONDUCTOR ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpu TTL-to-ECL — 3.5 ns tpu ECL-to-TTL • Low skew < ± 1 ns • Can operate on single +5V supply

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

MC10804

Abstract: MC10806 ao65
Contextual Info: MOTOROLA MC10804 MC10805 BIDIRECTIONAL TRANSCEIVER WITH LATCH The MC10804 and MC10805 are inverting bidirectional trans­ ceivers that interface MECL logic levels with TTL logic levels. Data can be transferred directly in either direction MECL -*•TTL or TTL

CY7B185

Abstract: CY7B922 clock buffer FITS CY7B991 CY7B992 EME-6300H SM23B CY7B991-LMB
Contextual Info: Qualification Report February, 1994 QTP# 92202&93462 Version 2.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B991 TTL CY7B992 (CMOS) QUALIFICATION REPORT February, 1994 Version 2.0 QTP # 92202/93462 PROGRAMMABLE SKEW CLOCK BUFFER CY7B991 (TTL) CY7B992 (CMOS) CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

Contextual Info: Processor Interface Components—QSpan User Manual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

ITT401AC

Abstract: SOIC-14
Contextual Info: SP4T SWITCH WITH DIRECT TTL CONTROL AND SINGLE POSITVE SUPPLY ITT401AC FEATURES • • • • • Single Positive Supply +8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION ADVANCED INFORMATION GND J3 GND J1

181-D

Abstract: AD 157 Y AD17 SCL23
Contextual Info: Processor Interface Components—QSpan User M anual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input

d15181

Abstract: QSpan AD899 Tundra QSpan 181-D AD17 qspan top mark
Contextual Info: Processor Interface Components—QSpan User M anual 4 Signals and DC Characteristics 4.1 Terminology The abbreviations used in this chapter are defined below. Two-state output Tristate output Bidirectional Input Output Open Drain Input with TTL threshold TTL Schmitt trigger input

j934

Contextual Info: SP8T Switch with Direct TTL Control and Single Positive Supply ITTS801AR FEATURES • • • • • ADVANCED INFORMATION TSSOP24 Single Positive Supply 8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION MAXIMUM RATINGS (T

Contextual Info: P54/74FCT3973C/D 3.3 VOLT OCTAL TRANSPARENT LATCHES 5.0 TO 3.3 VOLT TRANSLATOR FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Inputs and Outputs Interface with TTL Logic Levels ■ 3.3V ± 0.2V Power Supply and CMOS for Lowest

ax 3003

Abstract: meab 1N3064 1N916 M38510 76l70
Contextual Info: MIL-M-38510/28B USAF 2 August 1974-SUPERSEDING MIL-M-38510/28(USAF) 21 August 1972 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL TTL, LOW POWER SHIFT REGISTERS MONOLITHIC SILICON 1. SCOPE 1.1 Scope• This specification covers the requirements for monolithic silicon, TTL,

Contextual Info: P54/74FCT3157C/D — P54/74FCT3158C/D 3.3 VOLT DATA SELECTOR/MULTIPLEXER 7$ FEATURES Function and Drive Compatible with the Fastest TTL Logic Inputs and Outputs Interface with TTL Logic Levels 3.3V ± 0.2V Power Supply and CMOS for Lowest Power Dissipation

Contextual Info: SP4T Switch with Direct TTL Control and Single Positive Supply ITTS401AC FEATURES • • • • • ADVANCED INFORMATION SOIC 14 Single Positive Supply +8V Direct TTL input On-Chip Decoder Logic Low Power Consumption Non-Reflective Ports DESCRIPTION MAXIMUM RATINGS (T

Contextual Info: P54/74FCT3373C/D 3.3 VOLT OCTAL TRANSPARENT LATCHES WITH 3-STATE OUTPUTS FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Edge-rate Control Circuitry for Significantly Reduced Switching Noise Characteristics ■ Inputs and Outputs Interface with TTL Logic

Contextual Info: P54/74FCT3157C/D — P54/74FCT3158C/D 3.3 VOLT DATA SELECTOR/MULTIPLEXER FEATURES • Function and Drive Compatible with the Fastest TTL Logic ■ Inputs and Outputs Interface with TTL Logic Levels ■ 3.3V + 0.2V Power Supply and CMOS for Lowest Power Dissipation