TRISTATE BUFFER CMOS Search Results

Contextual Info: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down

AZP94

Contextual Info: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down

Contextual Info: 54FCT244 54FCT244 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS430 54FCT244 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT244 is an octal buffer and line driver with TRI-STATE outputs designed to be employed as a memory

Contextual Info: 54FCT540 54FCT540 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS431 54FCT540 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT540 is an octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and

Contextual Info: 54FCT541 54FCT541 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS424 54FCT541 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’FCT541 is an octal buffer and line driver with TRI-STATE outputs designed to be employed as a memory

Contextual Info: 54FCT241 54FCT241 Octal Buffer/Line Driver with -TRISTATE Outputs Literature Number: SNOS425 54FCT241 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The FCT241 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address

Contextual Info: PO11 ATL25 CMOS Gate Array cell data sheets 4.0 Description: Tristate output buffer, 2mA drive. Characterization: 25C, 3.3v, Nominal Process Cell area sites : 0.0 Pin caps(pF): AO=0.060, E0=0.060 Typical delay times (slope in ns/pF; intercept in ns; input transition = 0.600ns):

PO22

Abstract: PO-99 PO44 ATL35 PO33 PO55 CMOS GATE ARRAY AO40
Contextual Info: PO11 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Tristate output buffer, 2mA drive Truth Table: AO E0 PO11 E0 A0 E0 | P -X | Z 1 | 0 1 1 | 1 P E0 pchn2pad_x1 I1 AO AO gateP gateN outputDRVS1 I3 P I2 nchn2pad_x1 / $Revision: 1.35 $

Contextual Info: PO11 ATL35 CMOS Gate Array cell data sheets 1.0 DESCRIPTION: Tristate output buffer, 2mA drive Truth Table: AO E0 PO11 E0 A0 E0 | P -X | Z 1 | 0 1 1 | 1 P E0 pchn2pad_x1 I1 AO AO gateP gateN outputDRVS1 I3 P I2 nchn2pad_x1 / $Revision: 1.35 $

02-JUN

Abstract: CS0897 sot665 74AUP1G125GTR 74AUP1G125 A115-A C101 74AUP
Contextual Info: 74AUP1G125 Low power single tristate buffer Features • High speed: tPD = 6.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■

Contextual Info: 74AUP1G125 Low power single tristate buffer Features • High speed: tPD = 6.3 ns max. at VCC = 2.3 V ■ Power down protection on inputs and outputs ■ Balanced propagation delays: tPLH ≈ tPHL ■ Operating voltage range: VCC (opr) = 1.2 to 3.6 V ■

octal Bilateral Switches

Abstract: MM74HC14M MM74HC138M CD4025BCM MM74HC00M MM74HC74AM MM74HC125M MM74HC04M cd4046bcm cd4052bcm
Contextual Info: 1/3 CMOS LOGIC MM74HC SERIES MM74HCT/U SERIES • HIGH SPEED CMOS TECHNOLOGY, CMOS DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES Part Number Description • HIGH SPEED CMOS TECHNOLOGY, TTL DRIVE LEVELS, SPEED COMPARABLE TO 74LS SERIES SQP £ ea. Gates & Inverters

TEMIC PLD

Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
Contextual Info: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The

A/ATMEL 0843

Contextual Info: ATL80 - 0.8 µ I/O Buffer Cells Typical Delays at Tj = 25°C; Vdd = 5.0 V; Input Rise and Fall Times = 1 ns; Process = Nominal Sample of buffers composed of modular I/O building blocks Cell Name Description (Site Count) PBD2C 4 mA bidi CMOS buffer (1) PBD3C

T Flip-Flop

Abstract: national hct 4049 datasheet 74 act 574 e hct 4049 datasheet TBA 240 a 4514 v 4049 CMOS Inverter 4049 schmitt trigger hc 4051 HC 123A
Contextual Info: CMOS Logic KEY CMOS Logic Advanced CMOS FACT TM AC FACT Quiet Series TM (ACQ) FACT (ACT) FACT Quiet Series (ACTQ) FACT FCT VHC VHCT HC HCT T e available in JEDEC e e available in EIAJ Te e available in JEDEC and EIAJ w e available in wide format Tw e available in standard and

AO4L

Abstract: ld3p AO15A AO16A FD3S AO15AN AO23L BT8C datasheet MTC-35400 mux2*1
Contextual Info: MTC-35000 CMOS 0.5µ Standard Cell Library Services October ‘98 CMOS Family Features • Technology - 0.5µ CMOS for mixed analog 2 digital application - 0.5 micron CMOS transistors, triple layer metal, single or doble poly layer - Self-aligned twin tub Nand P-wells

Contextual Info: M T C -1 2 0 0 0 C M O S 1 .2 u Standard Cell Library Services CMOS Family Features • Technology: - 1.2 micron tw in -w ell CMOS process w ith polycide gates, double layer m etal, linear Ihin oxide capacitors and high ohmic resistors - Shrink capability to

Tri-State Buffer CMOS

Abstract: tristate buffer cmos tristate buffer active low 5962R9577201VXC Advanced TTL Logic ACS244MS ACS541MS HCTS240ADMSR HCTS240AHMSR HCTS240AKMSR
Contextual Info: HCTS240AMS Device Information Printer Friendly Version HCTS240AMS Driver, Buffer/Line, Inverter, Tri-State, TTL Inputs, Octal, Rad-Hard, High-Speed, CMOS, Logic Get Datasheet Ordering Information Price Status Temp. Package MSL SMD US $ 20 Ld Contact HCTS240ADMSR Active N/A 5962R9577201VRC

Contextual Info: M T C - 2 2 0 0 0 C M O S 0 .7 n Standard Cell Family Services CMOS Family Features • Technology: CMOS 0 .7 m icron, double or triple la y e r m etal digital or m ix e d a n a lo g /d ig ita l processes, featu rin g self­ aligned tw in tub N an d P w ells, polycide or polysilicon

16-LINE TO 4-LINE PRIORITY ENCODERS

Abstract: 32-Bit Parallel-IN Serial-OUT Shift Register RS flip flop cmos 16-to-4 line priority encoder RS flip flop DSTD190 CMOS Quad 2-Input NOR Gate encoder 74174 jk flip flop to d flip flop conversion T Flip-Flop
Contextual Info: CMOS PLD Designing with the Atmel-ViewPLD Development Tool Like the Atmel-ABEL software, the Atmel-ViewPLD development tool uses a popular industry-standard CAE development system. The development tool integrates the Viewlogic Workview software as the design environment with Data I/O’s

208-pin cpga

Contextual Info: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA last updated 5/15/2000 Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and

68-PIN

Abstract: 84-PIN cpga pinout 208-pin cpga
Contextual Info: Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed • ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and

Contextual Info: MM54HCT540/MM74HCT540 Inverting Octal TRI-STATE Buffer MM54HCT541/MM74HCT541 Octal TRI-STATE Buffer General Description These TRI-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed in­ verting and non-inverting buffers. They possess high drive

HXE12

Abstract: AMI500HXPF
Contextual Info: 0.5 Micron CMOS Pad Library Datasheets AMI500HXPF 5.0 Volt Section 4 Revision 1.1 Selection Guide AMI500HXPF 0.5 micron CMOS Pad Library PAD SELECTION GUIDE Input Drive Pieces Name Description IDCI3 IDCR0 IDCS3 IDCXx IDPX3 IDQC0 IDQC3 IDQS3 IDTS3 IDTXx Inverting, CMOS-level input buffer piece .4-5